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< img width = "186" height = "70" style = " margin: 10px 0px 10px 10px;" alt = "9086 logo" src = "readme_files/9086_design1.svg" >
A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
### Progress
* [ ] 8086
* [X] Executing code
* [X] Is Turing complete
* [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [X] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
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* [X] Has been successfully synthesized
### High level design overview
< img width = "700" style = " margin: 10px 0px 10px 10px;" alt = "9086 logo" src = "readme_files/9086_overview.svg" >
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### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk ](./common.mk )
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 12.0 OR ** (preferred)** Verilator : 5.016
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
After that you can run `make` on the top level directory and it should build everything and start the simulation
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### Synthesis and bitstream creation ( for FPGAs )
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Synthesis is based on Yosys. You need to select your board in [common.mk ](./common.mk ) which is the name of a directory inside inside [system/fpga\_config/ ](system/fpga_config/ ) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
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This list shows the software needed and the versions used during development
* yosys : 0.35
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
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Additionally, for ECP5 FPGAs:
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* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
* nextpnr : 0.6
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Additionally, for FPGAs using the [foboot ](https://github.com/im-tomu/foboot ) bootloader
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* dfu-util : 0.11
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### License and Copyright
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All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
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Efthymios Kritikos is the copyright owner for all files except the following:
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| File | Copyright owner | Original license |
| :--------------------------------------------------------: | :-------------: | :--------------: |
| system/fpga\_config/OrangeCrab\_r0.2.1/pin\_constraint.pcf | Greg Davill | MIT |
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### Version names
The version name consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
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A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.
