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22 Commits
v0 ... master

Author SHA1 Message Date
e38cb21738 check email change 2024-02-01 15:27:27 +00:00
df4e927d06 edits 2023-11-07 14:23:36 +00:00
54233baa70 edits 2023-11-07 13:50:50 +00:00
80a323118b edits 2023-11-07 13:50:18 +00:00
10f33ac651 edits 2023-11-07 13:48:36 +00:00
3c38505627 edits 2023-11-07 13:47:15 +00:00
61e0ee8e21 edits 2023-11-07 13:44:09 +00:00
a9ecc80990 edit 2023-11-07 13:31:17 +00:00
9c169882e7 test 2023-11-07 13:24:51 +00:00
440b55f4d0 Test 2023-11-02 00:11:50 +00:00
83aeab6c4e Test 2023-11-02 00:11:16 +00:00
e32ed7573b Test 2023-11-02 00:09:43 +00:00
127865f343 test 2023-11-02 00:00:23 +00:00
f7a9d9129c test 2023-11-01 23:59:45 +00:00
62c6a8823c test 2023-11-01 23:59:06 +00:00
f3025ff7b2 test 2023-11-01 23:58:30 +00:00
c38b09be75 test 2023-10-24 01:05:28 +01:00
698444b6e2 Test 2023-10-24 01:04:25 +01:00
fe1cff1170 More tests 2023-10-23 13:22:24 +01:00
95dc7a8d27 aaa 2023-05-16 14:05:06 +01:00
cd81f846a9 test main readme 2023-05-16 14:04:20 +01:00
c2d6e5d964 Test new readme 2023-05-04 03:18:59 +01:00
6 changed files with 801 additions and 38 deletions

View File

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### Project name test
<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="9086.svg">
Heading test
A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
### Progress
* [X] 8086
* [X] Executing code
* [X] Is Turing complete
* [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [ ] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
* [ ] Has been successfully synthesized
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.006
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.1
After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="9086_v0.2.0.svg">
### License
All parts of this project are licensed under the GNU General Public License version 3 or later
### Versions
The version consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the third milestone and has 2 bug fixes since the milestone was reached.
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<img width="140" height="52" align="left" style="float: left; margin: 0 10px 0 0;" alt="9086 logo" src="https://git.efthimiskritikos.com/Efthimis/Testing/raw/branch/master/9086.svg">
# 9086
<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
### Most instructions follow this format
| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit |
| ----- | --------- | ---- | --------------- | ------------ | ---- |
| OpCod | Direction | Size | Addressing mode | Register ID | Specific addressign mode|
A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
| Register ID | Register Name|
|:-------------:|:-------------:|
|0 0 0 |AL AX|
|0 0 1 |CL CX|
|0 1 0 |DL DX|
|0 1 1 |BL BX|
|1 0 0 |AH SP|
|1 0 1 |CH BP|
|1 1 0 |DH SI|
|1 1 1 |BH DI|
### Progress
* [ ] Not checked
* [ ] still checked
* [almost] checked
* [x] checked
* [ ] 8086
* [X] Executing code
* [X] Is Turing complete
* [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [X] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
* [X] Has been successfully synthesized
* [ ] Has a comprehensive testing framework
|.. |.. |.. |.. | O | D | I | T | S | Z |.. | A |.. | P |.. | C |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
This list shows the software needed and the versions used during development :
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
After that you can run `make` on the top level directory and it should build everything and start the simulation
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
These are the currently supported fpga boards:
* OrangeCrab r0.2.1
This list shows the software needed and the versions used during development :
* yosys : 0.35
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
Additionally, for ECP5 FPGAs:
* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
* nextpnr : 0.6
Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
* dfu-util : 0.11
### License and Copyright
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
Efthymios Kritikos is the copyright owner for all files except the following:
| File | Copyright owner | Original license |
| :--------------------------------------------------------: | :-------------: | :--------------: |
| system/fpga\_config/OrangeCrab\_r0.2.1/pin\_constraint.pcf | Greg Davill | MIT |
### Version names
The version name consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.

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<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
### Progress
* [ ] 8086
* [X] Executing code
* [X] Is Turing complete
* [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [X] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
* [ ] Has been successfully synthesized
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.008
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.3
After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview
This image is outdated. It was made for v0.1.0
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### License
All parts of this project are licensed under the GNU General Public License version 3 or later
### Version names
The version name consist of three numbers:
1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.