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(Tim) Efthimis Kritikos 2023-11-07 13:48:36 +00:00
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test.md
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@ -20,7 +20,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
@ -32,7 +32,7 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [common.mk](./common.mk) to the name of a directory inside [system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
This list shows the software needed and the versions used during development