103 lines
2.0 KiB
Verilog
103 lines
2.0 KiB
Verilog
`include "proc_state_def.v"
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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/* State */
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reg [3:0] state;
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reg instruction_finished;
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/* Registers */
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reg [19:0] ProgCount;
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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/* RESET LOGIC */
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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ProgCount=0;//TODO: Reset Vector
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ADD_INST=0;
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EXCEPTION=0;
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INC_INST=0;
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HALT=0;
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@(negedge clock);
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@(posedge clock);
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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/* Processor stages */
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reg ADD_INST,EXCEPTION,INC_INST;
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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CIR <= external_data_bus;
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ProgCount=ProgCount+1;
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state=`PROC_DE_STATE_ENTRY;
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end
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endcase
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end
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:
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HALT=1;
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`PROC_IF_STATE_ENTRY:begin
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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state=`PROC_IF_WRITE_CIR;
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end
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`PROC_DE_STATE_ENTRY:begin
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external_address_bus <= ProgCount; /*Remenance from IF*/
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case(CIR[15:10])
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6'b100000 : begin
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case (CIR[5:3])
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3'b000 :begin
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ADD_INST=1;
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state=`PROC_DE_LOAD_16_PARAM;
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end
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default:begin
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end
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6'b111111 : begin
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000 :begin
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INC_INST=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end else begin
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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default:begin
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EXCEPTION=1;
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end
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`PROC_DE_LOAD_16_PARAM:begin
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PARAM1 <= external_data_bus;
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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EXCEPTION=0;ADD_INST=0;INC_INST=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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end
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endmodule
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