`include "proc_state_def.v"

module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
/* State */
reg [3:0] state;
reg instruction_finished;

/* Registers */
reg [19:0] ProgCount;
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;

/* RESET LOGIC */
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		ProgCount=0;//TODO: Reset Vector
		ADD_INST=0;
		EXCEPTION=0;
		INC_INST=0;
		HALT=0;
		@(negedge clock);
		@(posedge clock);
		state=`PROC_IF_STATE_ENTRY;
	end
end

/* Processor stages */
reg ADD_INST,EXCEPTION,INC_INST;

always @(negedge clock) begin
	case(state)
		`PROC_IF_WRITE_CIR:begin
			CIR <= external_data_bus;
			ProgCount=ProgCount+1;
			state=`PROC_DE_STATE_ENTRY;
		end
	endcase
end

always @(posedge clock) begin
	case(state)
		`PROC_HALT_STATE:
			HALT=1;
		`PROC_IF_STATE_ENTRY:begin
			external_address_bus <= ProgCount;
			read <= 0;
			write <= 1;
			state=`PROC_IF_WRITE_CIR;
		end
		`PROC_DE_STATE_ENTRY:begin
			external_address_bus <= ProgCount; /*Remenance from IF*/
			case(CIR[15:10])
				6'b100000 : begin
					case (CIR[5:3])
						3'b000 :begin
							ADD_INST=1;
							state=`PROC_DE_LOAD_16_PARAM;
						end
						default:begin
							EXCEPTION=1;
							state=`PROC_EX_STATE_ENTRY;
						end
					endcase
				end
				6'b111111 : begin
					if (CIR[9:9] == 1 ) begin
						case (CIR[5:3])
							3'b000 :begin
								INC_INST=1;
								state=`PROC_EX_STATE_ENTRY;
							end
							default:begin
								EXCEPTION=1;
								state=`PROC_EX_STATE_ENTRY;
							end
						endcase
					end else begin
						EXCEPTION=1;
						state=`PROC_EX_STATE_ENTRY;
					end
				end
				default:begin
					EXCEPTION=1;
					state=`PROC_EX_STATE_ENTRY;
				end
			endcase
		end
		`PROC_DE_LOAD_16_PARAM:begin
			PARAM1 <= external_data_bus;
			ProgCount=ProgCount+1;
			state=`PROC_EX_STATE_ENTRY;
		end
		`PROC_EX_STATE_ENTRY:begin
			EXCEPTION=0;ADD_INST=0;INC_INST=0;
			state=`PROC_IF_STATE_ENTRY;
		end
	endcase
end

endmodule