5.5 KiB
ISA
Instructions vary from 1 to 6 bytes.
Instructions format
| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit |
|---|---|---|---|---|---|
| Opcode | D bit | W bit | MOD | REG | R/M |
-
D-bit : The register specified in REG field is a source register (D = 0) or destination register (D =1).
-
W-bit : Specifies whether the instruction operates on bytes (W = 0) or words (W = 1).
On some instructions:
- S-bit : An 8-bit 2's complement number. It can be extended to a 16-bit 2’s complement number internally depending on the W-bit
| S | W | Operation |
|---|---|---|
| 0 | 0 | 8bit operation |
| 0 | 1 | 16bit operation with 16bit immediate operand |
| 1 | 0 | invalid? |
| 1 | 1 | 8bit immediate operand extended to 16 signed internally |
-
V-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits
-
Z-bit : Used as a compare bit with the zero flag in conditional repeat and loop instructions. ex branch if zero is set or clear.
No instruction has parts of its opcode past the first 2 bytes I.e. all bytes after the first two are additional data bytes
The second byte of the instruction usually identifies the instruction's operands. The MOD (mode) field weather or not the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the REG field is used as an extension of the opcode. The function of R/M depends on how MOD. if MOD=11 (register-register mode) then R/M specifies the second Register, otherwise it specifies how the effective address in memory is calculated
| R/M | Memory indirect with no displacement [ 0 0 ] | Memory indirect with 8 bit displacement [ 0 1 ] | Memory indirect with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0 | Register Mode [ 1 1 ] W = 1 |
|---|---|---|---|---|---|
| 000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX |
| 001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX |
| 010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX |
| 011 | [BP] + [DI] | [BP] + [DI] + d8 | [BP] + [DI] + d16 | BL | BX |
| 100 | [SI] | [SI] + d8 | [SI] + d16 | AH | SP |
| 101 | [DI] | [DI] + d8 | [DI] + d16 | CH | BP |
| 110 | d16 (direct) | [BP] + d8 | [BP] + d16 | DH | SI |
| 111 | [BX] | [BX] + d8 | [BX] + d16 | BH | DI |
Example instructions:
| Bytecode | AT&T Syntax | meaning |
|---|---|---|
| 81 c0 aa 55 | add $0x55aa,%ax | add 0x55aa to register ax |
| 03 06 aa 55 | add 0x55aa,%ax | add the contents of memory location 0x55aa to register ax |
| fe c0 | inc %al | increment register al |
| ff c0 | inc %ax | increment register ax |
| 40 | inc %ax | increment register ax |
Flags
Flag register:
| .. | .. | .. | .. | O | D | I | T | S | Z | .. | A | .. | P | .. | C |
|---|
-
C - Carry flag : carry out or borrow into the high order bit (8bit/16bit)
-
P - Parity flag : set if result has even parity
-
A - Auxiliary flag : carry out from the low nibble to the high nibble or an equiv borrow. Used by decimal arithmetic instructions
-
Z - Zero flag : Set when result of Operation is zero
-
S - Sign flag : set if the high order bit of the result is 1. ie the sign of the result
-
T - Trap flag : Set the CPU into single step mode where it generates an interrupt after each instruction
-
I - Interrupt flag : 0: interrupts are masked
-
D - Direction flag : 1: string instructions decrement 0: they increment
-
O - Overflow flag : set on arithmetic overflow