540 lines
15 KiB
Verilog
540 lines
15 KiB
Verilog
/* processor.v - implementation of most functions of the 9086 processor
|
|
|
|
This file is part of the 9086 project.
|
|
|
|
Copyright (c) 2023 Efthymios Kritikos
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
|
|
|
`include "proc_state_def.v"
|
|
`include "alu_header.v"
|
|
`include "config.v"
|
|
`include "ucode_header.v"
|
|
`include "error_header.v"
|
|
|
|
//HALT: active high
|
|
//IOMEM: 1=IO 0=MEM
|
|
//write: active low
|
|
//read: active low
|
|
//reset: active low
|
|
|
|
module processor ( input clock, input reset, output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM, output reg HALT,output reg [`ERROR_BITS-1:0] ERROR);
|
|
|
|
/*** Global Definitions ***/
|
|
reg [`PROC_STATE_BITS-1:0] state;
|
|
|
|
/*############ Bus Interface Unit ############################################### */
|
|
|
|
wire [31:0] INSTRUCTION;
|
|
reg [1:0] BIU_NEXT_POSITION;
|
|
wire VALID_INSTRUCTION;
|
|
wire [15:0] INSTRUCTION_LOCATION;
|
|
reg [15:0] BIU_ADDRESS_INPUT;
|
|
wire [15:0] BIU_DATA;
|
|
reg biu_write_request;
|
|
reg biu_data_direction;
|
|
reg biu_read_request;
|
|
wire BIU_VALID_DATA;
|
|
|
|
BIU BIU(
|
|
clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
|
|
INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,BIU_NEXT_POSITION,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
|
|
state,SIMPLE_MICRO
|
|
);
|
|
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select?reg_read_port1_data:ALU_1O);
|
|
|
|
/*############ Decoder ########################################################## */
|
|
reg Wbit, Sbit, opcode_size;
|
|
wire DE_Wbit, DE_Sbit, DE_opcode_size;
|
|
wire [`PROC_STATE_BITS-1:0] next_state;
|
|
reg [2:0]RM;
|
|
wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
|
|
wire [15:0]DE_PARAM2;
|
|
wire [2:0]DE_IN_MOD;
|
|
wire [2:0]DE_RM;
|
|
wire [2:0]DE_OUT_MOD;
|
|
wire [`ERROR_BITS-1:0] DE_ERROR;
|
|
wire DE_HALT;
|
|
wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
|
|
wire [11:0]DE_REGISTER_CONTROL;
|
|
wire [2:0]INSTRUCTION_INFO;
|
|
wire [`ERROR_BITS:0]DECODER_SIGNALS;
|
|
wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
|
|
|
|
reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
|
|
wire [2:0] DE_instruction_size;
|
|
reg instruction_size_init;
|
|
//TODO : remove completely?
|
|
/* verilator lint_off UNUSEDSIGNAL */
|
|
wire [2:0] instruction_size;
|
|
/* verilator lint_on UNUSEDSIGNAL */
|
|
assign instruction_size = instruction_size_init ? 3'b010 : DE_instruction_size;
|
|
reg memio_address_select;
|
|
wire DE_memio_address_select;
|
|
wire DE_MEM_OR_IO;
|
|
reg MEM_OR_IO;
|
|
wire [1:0] DE_in_alu1_sel1;
|
|
wire [1:0] DE_in_alu1_sel2;
|
|
reg [`ALU_OP_BITS-1:0] DE_ALU_1OP;
|
|
decoder decoder(
|
|
.CIR(INSTRUCTION[31:16]),
|
|
.FLAGS(FLAGS),
|
|
.INSTRUCTION_INFO(INSTRUCTION_INFO),
|
|
.DECODER_SIGNALS(DECODER_SIGNALS),
|
|
.next_state(next_state),
|
|
.IN_MOD(DE_IN_MOD),
|
|
.RM(DE_RM),
|
|
.PARAM1(DE_PARAM1),
|
|
.PARAM2(DE_PARAM2),
|
|
.in_alu1_sel1(DE_in_alu1_sel1),
|
|
.in_alu1_sel2(DE_in_alu1_sel2),
|
|
.OUT_MOD(DE_OUT_MOD),
|
|
.REGISTER_FILE_CONTROL(DE_REGISTER_CONTROL),
|
|
.ALU_1OP(DE_ALU_1OP),
|
|
.seq_addr_entry(ucode_seq_addr_entry),
|
|
.SIMPLE_MICRO(SIMPLE_MICRO),
|
|
.seq_addr_input(ucode_seq_addr),
|
|
.instruction_size(DE_instruction_size),
|
|
.memio_address_select(DE_memio_address_select),
|
|
.MEM_OR_IO(DE_MEM_OR_IO)
|
|
);
|
|
|
|
assign DE_Wbit=INSTRUCTION_INFO[2:2];
|
|
assign DE_Sbit=INSTRUCTION_INFO[1:1];
|
|
assign DE_opcode_size=INSTRUCTION_INFO[0:0];
|
|
|
|
assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
|
|
assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
|
|
assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];
|
|
|
|
assign DE_HALT=DECODER_SIGNALS[0:0];
|
|
assign DE_ERROR=DECODER_SIGNALS[`ERROR_BITS:1];
|
|
|
|
reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
|
|
|
|
/*############ REGISTERS ########################################################## */
|
|
|
|
reg [15:0] PARAM1;
|
|
reg [15:0] PARAM2;
|
|
|
|
// verilator lint_off UNDRIVEN
|
|
reg [15:0] FLAGS;
|
|
// verilator lint_on UNDRIVEN
|
|
|
|
//Architectural Register file
|
|
reg [3:0] reg_write_addr;
|
|
wire [15:0] reg_write_data;
|
|
reg reg_write_we;
|
|
reg [3:0] reg_read_port1_addr;
|
|
reg [15:0] reg_read_port1_data;
|
|
reg [3:0] reg_read_port2_addr;
|
|
reg [15:0] reg_read_port2_data;
|
|
reg [1:0] reg_write_in_sel;
|
|
mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
|
|
ALU_1O,
|
|
16'hz,
|
|
16'hz,
|
|
16'hz,
|
|
reg_write_in_sel,
|
|
reg_write_data);
|
|
register_file register_file(
|
|
.write_port1_addr(reg_write_addr),
|
|
.write_port1_data(reg_write_data),
|
|
.write_port1_we(reg_write_we),
|
|
.read_port1_addr(reg_read_port1_addr),
|
|
.read_port1_data(reg_read_port1_data),
|
|
.read_port2_addr(reg_read_port2_addr),
|
|
.read_port2_data(reg_read_port2_data)
|
|
);
|
|
|
|
reg [15:0] ProgCount;
|
|
|
|
/*############ ALU / Execution units ########################################################## */
|
|
// ALU 1
|
|
reg [1:0] in_alu1_sel1;
|
|
reg [1:0] in_alu1_sel2;
|
|
/* OUT_MOD : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
|
|
reg [2:0] IN_MOD;
|
|
reg [2:0] OUT_MOD;
|
|
|
|
mux4 #(.WIDTH(16)) MUX16_1A(
|
|
/*0*/ PARAM1,
|
|
/*1*/ reg_read_port1_data,
|
|
/*2*/ ProgCount[15:0],
|
|
/*3*/ 16'd0, /*0 Constant*/
|
|
in_alu1_sel1,
|
|
ALU_1A);
|
|
|
|
mux4 #(.WIDTH(16)) MUX16_1B(
|
|
/*0*/ PARAM2,
|
|
/*1*/ reg_read_port2_data,
|
|
/*2*/ ProgCount[15:0],
|
|
/*3*/ 16'd0, /*0 Constant*/
|
|
in_alu1_sel2,
|
|
ALU_1B);
|
|
|
|
wire [15:0] ALU_1A;
|
|
wire [15:0] ALU_1B;
|
|
wire [15:0] ALU_1O;
|
|
reg [`ALU_OP_BITS-1:0]ALU_1OP;
|
|
wire [7:0] ALU_1FLAGS;
|
|
ALU ALU1(
|
|
.A(ALU_1A),
|
|
.B(ALU_1B),
|
|
.OUT(ALU_1O),
|
|
.op(ALU_1OP),
|
|
.FLAGS(ALU_1FLAGS),
|
|
.Wbit(Wbit)
|
|
);
|
|
|
|
/*############ Processor state machine ########################################################## */
|
|
|
|
/*** RESET LOGIC ***/
|
|
/* verilator lint_off MULTIDRIVEN */
|
|
always @(negedge reset) begin
|
|
state <= `PROC_HALT_STATE; //TODO: race condition ??
|
|
end
|
|
always @(posedge reset) begin
|
|
state <= `PROC_RESET;
|
|
end
|
|
/* verilator lint_on MULTIDRIVEN */
|
|
|
|
/*** Processor stages ***/
|
|
`define unimpl_addressing_mode state <= `PROC_DE_STATE_ENTRY;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
|
|
|
|
wire [2:0] instr_end;
|
|
InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},instr_end);
|
|
|
|
reg [23:0] INSTRUCTION_BUFFER;
|
|
|
|
always @(posedge clock) begin
|
|
case(state)
|
|
`PROC_RESET:begin
|
|
BIU_NEXT_POSITION <= 0;
|
|
ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
|
|
HALT <= 0;
|
|
ERROR <= `ERR_NO_ERROR;
|
|
SIMPLE_MICRO <= 0;
|
|
reg_write_we <= 1;
|
|
instruction_size_init <= 1;
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
reg_write_in_sel <= 2'b00; //only got wirtten in IF
|
|
biu_write_request <= 0;
|
|
biu_data_direction <= 0;
|
|
biu_read_request <= 0;
|
|
end
|
|
`PROC_HALT_STATE:begin
|
|
end
|
|
`PROC_DE_STATE_ENTRY:begin
|
|
reg_write_we <= 1;
|
|
if(VALID_INSTRUCTION==1) begin
|
|
if(SIMPLE_MICRO==0)begin
|
|
/*This flag is set at reset and jump because
|
|
* at IF we need to know the size of the
|
|
* previous instruction (specifically if it was
|
|
* a single byte and the value would be
|
|
* incorrect in both cases. So when it gets
|
|
* set reset it only at the start of the next
|
|
* 8086 instruction */
|
|
instruction_size_init <= 0;
|
|
|
|
/* We cannot set these directly within
|
|
* microcode so don't overwrite useful values
|
|
* each tie the next microcode is executed.
|
|
* Note this still allows to set initial values
|
|
* at the start of the microcode */
|
|
PARAM1 <= DE_PARAM1;
|
|
PARAM2 <= DE_PARAM2;
|
|
`ifdef DEBUG_PC_ADDRESS
|
|
$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
|
|
`endif
|
|
ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
|
|
INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
|
|
end
|
|
IN_MOD <= DE_IN_MOD;
|
|
OUT_MOD <= DE_OUT_MOD;
|
|
RM <= DE_RM;
|
|
ERROR <= DE_ERROR;
|
|
HALT <= DE_HALT;
|
|
Wbit <= DE_Wbit;
|
|
Sbit <= DE_Sbit;
|
|
opcode_size <= DE_opcode_size;
|
|
memio_address_select<=DE_memio_address_select;
|
|
reg_read_port1_addr <= DE_reg_read_port1_addr;
|
|
reg_read_port2_addr <= DE_reg_read_port2_addr;
|
|
reg_write_addr <= DE_reg_write_addr;
|
|
MEM_OR_IO <= DE_MEM_OR_IO;
|
|
in_alu1_sel1 <= DE_in_alu1_sel1;
|
|
in_alu1_sel2 <= DE_in_alu1_sel2;
|
|
ALU_1OP <= DE_ALU_1OP;
|
|
|
|
if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
|
|
/*switch to microcode decoding*/
|
|
ucode_seq_addr <= ucode_seq_addr_entry;
|
|
SIMPLE_MICRO <= 1;
|
|
/*keep state the same and rerun decode this time with all the data from the microcode rom*/
|
|
BIU_NEXT_POSITION <= 2'b00;
|
|
end else begin
|
|
state <= next_state;
|
|
if ( SIMPLE_MICRO == 0 ) begin
|
|
BIU_NEXT_POSITION <= 2'b00;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
`PROC_DE_LOAD_REG_TO_PARAM:begin
|
|
PARAM2<=reg_read_port2_data;
|
|
case(IN_MOD)
|
|
3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
|
|
default: state <= `PROC_EX_STATE_ENTRY;
|
|
endcase
|
|
end
|
|
`PROC_DE_LOAD_8_PARAM:begin
|
|
if(opcode_size==0)begin
|
|
if({Sbit,Wbit}==2'b11)begin
|
|
/*signed "16bit" read*/
|
|
PARAM1 <= {{8{INSTRUCTION_BUFFER[23:23]}},INSTRUCTION_BUFFER[23:16]};
|
|
end else begin
|
|
PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
|
|
end
|
|
case(IN_MOD)
|
|
3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
|
|
default: state <= `PROC_EX_STATE_ENTRY;
|
|
endcase
|
|
end else begin
|
|
if({Sbit,Wbit}==2'b11)begin
|
|
/*signed "16bit" read*/
|
|
PARAM1 <= {{8{INSTRUCTION_BUFFER[15:15]}},INSTRUCTION_BUFFER[15:8]};
|
|
end else begin
|
|
PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
|
|
end
|
|
end
|
|
case(IN_MOD)
|
|
3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
|
|
default: state <= `PROC_EX_STATE_ENTRY;
|
|
endcase
|
|
end
|
|
`PROC_DE_LOAD_16_PARAM:begin
|
|
if(opcode_size==0)begin
|
|
PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
|
|
PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8];
|
|
end else begin
|
|
PARAM1[15:8] <= INSTRUCTION_BUFFER[7:0];
|
|
PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
|
|
end
|
|
case(IN_MOD)
|
|
3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
|
|
default: state <= `PROC_EX_STATE_ENTRY;
|
|
endcase
|
|
end
|
|
`PROC_MEMIO_READ:begin
|
|
/*Decode MOD R/M, read the data and place it to PARAM1*/
|
|
case (IN_MOD)
|
|
3'b000,
|
|
3'b001,
|
|
3'b010:begin
|
|
case (RM)
|
|
3'b000:begin
|
|
/*[BX]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b001:begin
|
|
/*[BX]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b010:begin
|
|
/*[BP]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b011:begin
|
|
/*[BP]+[DI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b100:begin
|
|
/*[SI]*/
|
|
reg_read_port1_addr <= 4'b1110;
|
|
state <= `PROC_MEMIO_READ_SETADDR;
|
|
end
|
|
3'b101:begin
|
|
/*[DI]*/
|
|
reg_read_port1_addr <= 4'b1111;
|
|
state <= `PROC_MEMIO_READ_SETADDR;
|
|
end
|
|
3'b110:begin
|
|
/*d16 */
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b111:begin
|
|
/*[BX]*/
|
|
reg_read_port1_addr <= 4'b1011;
|
|
state <= `PROC_MEMIO_READ_SETADDR;
|
|
end
|
|
endcase
|
|
if(IN_MOD!=3'b000)begin
|
|
/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
|
|
`unimpl_addressing_mode;
|
|
end
|
|
end
|
|
3'b110:begin /* SP Indirect read*/
|
|
reg_read_port1_addr <= 4'b1100;
|
|
state <= `PROC_MEMIO_READ_SETADDR;
|
|
end
|
|
default:begin
|
|
`unimpl_addressing_mode
|
|
end
|
|
endcase
|
|
end
|
|
`PROC_MEMIO_READ_SETADDR:begin
|
|
if(memio_address_select==0)
|
|
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
|
|
else
|
|
BIU_ADDRESS_INPUT <= ALU_1O;
|
|
|
|
if ( BIU_VALID_DATA == 1 ) begin
|
|
state <= `PROC_EX_STATE_ENTRY;
|
|
PARAM2 <= BIU_DATA;
|
|
biu_read_request <= 0;
|
|
biu_data_direction <= 0;
|
|
end else begin
|
|
biu_data_direction <= 1;
|
|
biu_read_request <= 1;
|
|
end
|
|
end
|
|
`PROC_NEXT_INSTRUCTION:begin
|
|
/*necessary for biu to see we went on another state from decode to give us a new instruction*/
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
end
|
|
`PROC_EX_STATE_ENTRY:begin
|
|
FLAGS[7:0] <= ALU_1FLAGS[7:0];
|
|
case(OUT_MOD)
|
|
3'b000,
|
|
3'b001,
|
|
3'b010 : begin
|
|
if(memio_address_select==1)
|
|
state <= `PROC_MEMIO_WRITE;
|
|
else
|
|
case (RM) /* Duplicate code with write... */
|
|
3'b000:begin
|
|
/*[BX]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b001:begin
|
|
/*[BX]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b010:begin
|
|
/*[BP]+[SI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b011:begin
|
|
/*[BP]+[DI]*/
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b100:begin
|
|
/*[SI]*/
|
|
reg_read_port1_addr <= 4'b1110;
|
|
state <= `PROC_MEMIO_WRITE;
|
|
end
|
|
3'b101:begin
|
|
/*[DI]*/
|
|
reg_read_port1_addr <= 4'b1111;
|
|
state <= `PROC_MEMIO_WRITE;
|
|
end
|
|
3'b110:begin
|
|
/*d16 */
|
|
`unimpl_addressing_mode
|
|
end
|
|
3'b111:begin
|
|
/*[BX]*/
|
|
reg_read_port1_addr <= 4'b1011;
|
|
state <= `PROC_MEMIO_WRITE;
|
|
end
|
|
endcase
|
|
end
|
|
3'b011:begin
|
|
reg_write_we <= 0;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b100:begin /*No output*/
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b101:begin /* Program Counter*/
|
|
BIU_ADDRESS_INPUT <= ALU_1O[15:0];
|
|
BIU_NEXT_POSITION <= 2'b10;
|
|
instruction_size_init <= 1;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b110:begin /* SP Indirect write*/
|
|
reg_read_port1_addr <= 4'b1100;
|
|
state <= `PROC_MEMIO_WRITE;
|
|
end
|
|
3'b111:begin /* Write to PRAM1 (for microcode calculations) */
|
|
PARAM1 <= ALU_1O;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
default:begin
|
|
`unimpl_addressing_mode
|
|
end
|
|
endcase
|
|
end
|
|
`PROC_MEMIO_WRITE:begin
|
|
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
|
|
/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
|
|
|
|
biu_write_request <= 1;
|
|
|
|
if(memio_address_select==0)
|
|
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
|
|
else
|
|
BIU_ADDRESS_INPUT <= ALU_1O;
|
|
|
|
if (write == 0) begin
|
|
biu_write_request <= 0;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
|
|
end
|
|
`PROC_NEXT_MICROCODE:begin
|
|
ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
|
|
if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
|
|
/*Finished microcode*/
|
|
SIMPLE_MICRO <= 0;
|
|
end
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
reg_write_we <= 1;
|
|
end
|
|
default:begin
|
|
end
|
|
endcase
|
|
end
|
|
`undef unimpl_addressing_mode
|
|
|
|
|
|
endmodule
|