(Tim) Efthimis Kritikos e06c0eeaa0 Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!		2023-11-12 04:04:56 +00:00
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fpga_config/OrangeCrab_r0.2.1	Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!	2023-11-09 22:10:55 +00:00
peripherals	Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!	2023-11-09 22:10:55 +00:00
alu_header.v	Added partial support for the software interrupt INT instruction	2023-03-08 07:26:28 +00:00
alu.v	More small fixes	2023-11-04 08:31:05 +00:00
biu.v	Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!	2023-11-06 05:36:04 +00:00
boot_code.asm	Improved DOS char print code	2023-03-14 07:20:30 +00:00
config.v	The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality	2023-11-06 08:13:36 +00:00
decoder.v	Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!	2023-11-12 04:04:56 +00:00
error_header.v	First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching	2023-05-07 13:34:15 +01:00
exec_state_def.v	Removed more "conflicting driver" issues with yet more performance penalties...	2023-11-04 15:33:23 +00:00
execute.v	fixed more driver conflicts	2023-11-06 01:35:48 +00:00
general.v	Cleaned up some pieces of code and fixed a bug	2023-05-04 00:49:04 +01:00
Makefile	Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!	2023-11-12 04:04:56 +00:00
memory.v	The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality	2023-11-06 08:13:36 +00:00
processor.v	Removed all instances of inout since from what i understand it's mostly synthesisable	2023-11-02 21:48:12 +00:00
registers.v	Removed probably unnecessary high impedance case yosys was complaining about in registers.v	2023-11-12 03:13:22 +00:00
system.v	Added back removed warnings to verilator since we have now fixed those issues	2023-11-12 00:07:33 +00:00
testbench.cpp	Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation	2023-11-04 11:04:22 +00:00
testbench.v	Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation	2023-11-04 11:04:22 +00:00
ucode_header.v	Added partial support for the software interrupt INT instruction	2023-03-08 07:26:28 +00:00
ucode.txt	Changed slogan and cleaned up some small pieces of code	2023-05-23 16:18:33 +01:00
verilator_makefile	Removed erroneous file and run aspell	2023-03-21 14:51:39 +00:00