9086/system/fpga_config/OrangeCrab_r0.2.1/README.md

The OrangeCrab r0.2.1 has been configured with an I2C bus controller and LiteDRAM for the DDR3 memory that is on-board.

This is a block diagram of the system:

and inside the FPGA:

and this is the hardware setup during development:

You can find some configuration options in the ./config.mk