32 lines
1.0 KiB
Verilog
32 lines
1.0 KiB
Verilog
/* general.v - Pieces of code that can be used by multiple other modules
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module mux4 (in1,in2,in3,in4, sel,out);
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input [1:0] sel;
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parameter WIDTH=16;
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input [WIDTH-1:0] in1,in2,in3,in4;
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output [WIDTH-1:0] out;
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assign out = (sel == 'b00) ? in1 :
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(sel == 'b01) ? in2 :
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(sel == 'b10) ? in3 :
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in4;
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endmodule
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