/* processor.v - implementation of most functions of the 9086 processor

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "exec_state_def.v"
`include "alu_header.v"
`include "config.v"
`include "ucode_header.v"
`include "error_header.v"

//HALT: active high
//IOMEM: 1=IO  0=MEM
//write: active low
//read: active low
//reset: active low

`define PROC_STATE_BITS		3
`define PROC_RESET		3'b000
`define PROC_DE_STATE_ENTRY	3'b001
`define PROC_WAIT		3'b010
`define PROC_HALT		3'b011

module processor ( input clock, input reset, output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM, output reg HALT,output [`ERROR_BITS-1:0] ERROR);

/* If there is an error either from the decoder or execution unit set it to ERROR */
assign ERROR=(DE_ERROR_sampled!=`ERR_NO_ERROR)?DE_ERROR_sampled:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;

/*** Global Definitions ***/
reg [`PROC_STATE_BITS-1:0] state;

/*############ Execution Unit ################################################## */
reg [1:0] in_alu_sel1;
reg [1:0] in_alu_sel2;

wire [`EXEC_STATE_BITS-1:0] exec_state;

reg valid_exec_data;

wire [`ERROR_BITS-1:0] EXEC_ERROR;

wire use_exec_reg_addr;

wire [3:0] EXEC_reg_read_port1_addr;
reg [2:0] IN_MOD,OUT_MOD;
reg [`EXEC_STATE_BITS-1:0] exec_state_init;
reg [`ALU_OP_BITS-1:0] ALU_OP;
wire [15:0] ALU_O;
wire [7:0]EXEC_FLAGS;
reg [15:0] PARAM1_INIT;
reg [15:0] PARAM2_INIT;
reg set_initial_values;

execute_unit execute_unit (
	/*    GENERAL    */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
	/*               */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
	/*               */ ,set_initial_values
	/*     PARAM     */ ,PARAM1_INIT,PARAM2_INIT
	/* STATE CONTROL */ ,exec_state, exec_state_init
        /*  ALU CONTROL  */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
	/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
	/*     FLAFS     */ ,EXEC_FLAGS
	/*      BIU      */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
		 );

/*############ Bus Interface Unit ############################################### */

wire [31:0] INSTRUCTION;
wire biu_jump_req;
wire VALID_INSTRUCTION;
wire [15:0] INSTRUCTION_LOCATION;
wire [15:0] BIU_ADDRESS_INPUT;
wire [15:0] BIU_DATA;
wire biu_write_request;
wire biu_data_direction;
wire biu_read_request;
wire BIU_VALID_DATA;

BIU BIU(
	clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
	INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
	state,SIMPLE_MICRO
);
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);

/*############ Decoder ########################################################## */
reg Wbit, Sbit, opcode_size;
wire DE_Wbit, DE_Sbit, DE_opcode_size;
wire [`EXEC_STATE_BITS-1:0] next_state;
reg [2:0]RM;
wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
wire [15:0]DE_PARAM2;
wire [2:0]DE_IN_MOD;
wire [2:0]DE_RM;
wire [2:0]DE_OUT_MOD;
wire [`ERROR_BITS-1:0] DE_ERROR;
wire DE_HALT;
wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
wire [11:0]DE_REGISTER_CONTROL;
wire [2:0]INSTRUCTION_INFO;
wire [`ERROR_BITS:0]DECODER_SIGNALS;
wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;

reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
//TODO : remove completely?
reg  memio_address_select;
wire DE_memio_address_select;
wire DE_MEM_OR_IO;
reg MEM_OR_IO;
wire [1:0] DE_in_alu_sel1;
wire [1:0] DE_in_alu_sel2;
reg [`ALU_OP_BITS-1:0] DE_ALU_OP;
decoder decoder(
	.CIR(INSTRUCTION[31:16]),
	.FLAGS(FLAGS),
	.INSTRUCTION_INFO(INSTRUCTION_INFO),
	.DECODER_SIGNALS(DECODER_SIGNALS),
	.next_state(next_state),
	.IN_MOD(DE_IN_MOD),
	.RM(DE_RM),
	.PARAM1(DE_PARAM1),
	.PARAM2(DE_PARAM2),
	.in_alu_sel1(DE_in_alu_sel1),
	.in_alu_sel2(DE_in_alu_sel2),
	.OUT_MOD(DE_OUT_MOD),
	.REGISTER_FILE_CONTROL(DE_REGISTER_CONTROL),
	.ALU_1OP(DE_ALU_OP),
	.seq_addr_entry(ucode_seq_addr_entry),
	.SIMPLE_MICRO(SIMPLE_MICRO),
	.seq_addr_input(ucode_seq_addr),
	.memio_address_select(DE_memio_address_select),
	.MEM_OR_IO(DE_MEM_OR_IO)
);

assign DE_Wbit=INSTRUCTION_INFO[2:2];
assign DE_Sbit=INSTRUCTION_INFO[1:1];
assign DE_opcode_size=INSTRUCTION_INFO[0:0];

assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];

assign DE_HALT=DECODER_SIGNALS[0:0];
assign DE_ERROR=DECODER_SIGNALS[`ERROR_BITS:1];
reg [`ERROR_BITS-1:0] DE_ERROR_sampled;

reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;

/*############ REGISTERS ########################################################## */


// verilator lint_off UNDRIVEN
reg [15:0] FLAGS;
// verilator lint_on UNDRIVEN

//Architectural Register file
reg [3:0] reg_write_addr;
wire [15:0] reg_write_data;
wire reg_write_we;
wire [3:0] reg_read_port1_addr;
reg [15:0] reg_read_port1_data;
reg [3:0] reg_read_port2_addr;
reg [15:0] reg_read_port2_data;
reg [1:0] reg_write_in_sel;

mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
	ALU_O,
	16'hz,
	16'hz,
	16'hz,
	reg_write_in_sel,
	reg_write_data);

register_file register_file(
	.write_port1_addr(reg_write_addr),
	.write_port1_data(reg_write_data),
	.write_port1_we(reg_write_we),
	.read_port1_addr(reg_read_port1_addr),
	.read_port1_data(reg_read_port1_data),
	.read_port2_addr(reg_read_port2_addr),
	.read_port2_data(reg_read_port2_data)
);

assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : reg_read_port1_addr_latched;

reg [15:0] ProgCount;

/*############ Processor state machine ########################################################## */
reg [3:0] reg_read_port1_addr_latched;

/*** RESET LOGIC ***/
/* verilator lint_off MULTIDRIVEN */
always @(negedge reset) begin
	state <= `PROC_HALT; //TODO: race condition ??
end
always @(posedge reset) begin
	state <= `PROC_RESET;
end
/* verilator lint_on MULTIDRIVEN */

/*** Processor stages ***/

wire [2:0] instr_end;
InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},instr_end);

reg [23:0] INSTRUCTION_BUFFER;


always @(posedge clock) begin
	case(state)
		`PROC_RESET:begin
			ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
			HALT <= 0;
			SIMPLE_MICRO <= 0;
			state <= `PROC_DE_STATE_ENTRY;
			reg_write_in_sel <= 2'b00; //only got wirtten in IF
		end
		`PROC_DE_STATE_ENTRY:begin
			if(VALID_INSTRUCTION==1) begin
				if(SIMPLE_MICRO==0)begin
					/* We cannot set these directly within
					* microcode so don't overwrite useful values
					* each tie the next microcode is executed.
					* Note this still allows to set initial values
					* at the start of the microcode */
					PARAM1_INIT <= DE_PARAM1;
					PARAM2_INIT <= DE_PARAM2;
					`ifdef DEBUG_PC_ADDRESS
						$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
					`endif
					ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
					INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
					set_initial_values<=0;
				end
				DE_ERROR_sampled <= DE_ERROR;
				IN_MOD <= DE_IN_MOD;
				OUT_MOD <= DE_OUT_MOD;
				RM <= DE_RM;
				HALT <= DE_HALT;
				Wbit <= DE_Wbit;
				Sbit <= DE_Sbit;
				opcode_size <= DE_opcode_size;
				memio_address_select<=DE_memio_address_select;
				reg_read_port1_addr_latched <= DE_reg_read_port1_addr;
				reg_read_port2_addr <= DE_reg_read_port2_addr;
				reg_write_addr <= DE_reg_write_addr;
				MEM_OR_IO <= DE_MEM_OR_IO;
				in_alu_sel1 <= DE_in_alu_sel1;
				in_alu_sel2 <= DE_in_alu_sel2;
				ALU_OP <= DE_ALU_OP;
				if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
					/*switch to microcode decoding*/
					ucode_seq_addr <= ucode_seq_addr_entry;
					SIMPLE_MICRO <= 1;
					/*keep state the same and rerun decode this time with all the data from the microcode rom*/
				end else begin
					valid_exec_data <= 1;
					exec_state_init <= next_state;
					state <= `PROC_WAIT;
				end
			end
		end
		`PROC_WAIT:begin
			set_initial_values<=1;
			if( exec_state == `EXEC_DONE ) begin
				FLAGS[7:0] <= EXEC_FLAGS; //don't set all of them all the time!
				valid_exec_data<=0;
				state <= `PROC_DE_STATE_ENTRY;
				if(SIMPLE_MICRO == 1 ) begin
					ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
					if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
						/*Finished microcode*/
						SIMPLE_MICRO <= 0;
					end
				end
			end
		end
		`PROC_HALT:begin
		end
		default:begin
		end
	endcase
end


endmodule