232 lines
6.0 KiB
Verilog
232 lines
6.0 KiB
Verilog
/* system.v - A basic test system with memory and IO for the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`timescale 1ns/1ps
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`include "error_header.v"
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`include "config.v"
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module system ( input clock,input reset, output [19:0]address_bus, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
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`ifdef CALCULATE_IPC
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wire new_instruction;
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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wire unsigned [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT;
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wire VALID_INSTRUCTION_STAT,jump_req;
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`endif
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wire [15:0]data_bus_read_CPU,data_bus_write_CPU;
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assign data_bus_read_CPU=(IOMEM==0)?data_bus_read_RAM:data_bus_IO;
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assign data_bus_write=data_bus_write_CPU;
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wire wait_state=1'b0;
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processor p(
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/* MISC */ clock,reset,HALT,ERROR
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/* MEMORY / IO */ ,address_bus,data_bus_read_CPU,data_bus_write_CPU,wait_state,rd,wr,BHE,IOMEM
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,new_instruction
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT, jump_req
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`endif
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);
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wire [15:0] data_bus_read_RAM;
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doublemem #(.RAM_SIZE_IN_BYTES(65536)) sysmem(address_bus[15:0],data_bus_read_RAM,data_bus_write_CPU,rd,wr,BHE,IOMEM,clock);
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`ifdef OUTPUT_JSON_STATISTICS
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string stats_name,version,commit;
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integer json_file_descriptor;
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`endif
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`ifndef YOSYS
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string waveform_name;
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`endif
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initial begin
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`ifndef SYNTHESIS
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p,cycles);
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end
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`ifdef OUTPUT_JSON_STATISTICS
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if(!$value$plusargs("VERSION=%s",version)) version="unkown";
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if(!$value$plusargs("COMMIT=%s",commit)) commit="unkown";
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if($value$plusargs("STATS=%s",stats_name))begin
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json_file_descriptor=$fopen(stats_name,"w");
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$fdisplay(json_file_descriptor,"{\n\"L1_size\":%0d,\n\"9086 verison\":\"%s\",\n\"latest commit\":\"%s\",\n\"Cycles\":[",$rtoi($pow(2,`L1_CACHE_SIZE)),version,commit);
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first_json_cycle = 1;
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end else
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json_file_descriptor=0;
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`endif
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sane=0;
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finish=0;
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`endif
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end
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//integer killswitch=0;
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//always @(posedge clock) begin
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// killswitch <= killswitch +1;
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// if( killswitch == 20000 )begin
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// if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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// $writememh(memdump_name, system.sysmem.memory,0,32767);
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// end
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// $finish;
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// end
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//end
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`ifdef OUTPUT_JSON_STATISTICS
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reg first_json_cycle;
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always @(negedge clock)begin
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if(finish < 2 && json_file_descriptor!=0 && sane)begin
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$fdisplay(json_file_descriptor,"%s{\"C\":%0d,\"L1\":%0d,\"VDI\":%0d,\"JMP\":%0d}",first_json_cycle?"":",",cycles,L1_SIZE_STAT,VALID_INSTRUCTION_STAT,jump_req);
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first_json_cycle <= 0;
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end
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end
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`endif
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reg [15:0]data_bus_IO;
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`ifndef SYNTHESIS
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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$write("%s" ,data_bus_write[15:8]);
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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$display("\x1b[7mLed turned on\x1b[m\n");
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else
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$display("\x1b[7mLed turned off\x1b[m\n");
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end
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end
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always @(negedge rd) begin
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if(IOMEM==1'b1 && address_bus[7:1]==7'h10 )begin // 0xABCD on address 0x20
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data_bus_IO<=16'hABCD;
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end else begin
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data_bus_IO<=16'h0000;
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end
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end
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`endif
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`ifdef CALCULATE_IPC
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/* verilator lint_off MULTIDRIVEN */
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reg [128:0] instruction_count;
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/* verilator lint_on MULTIDRIVEN */
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always @(new_instruction) begin
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instruction_count<=instruction_count+1;
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end
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`endif
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`ifndef SYNTHESIS
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`ifdef OUTPUT_JSON_STATISTICS
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reg [128:0] instruction_count_temp;
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`endif
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string memdump_name;
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always @(posedge HALT) begin
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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/* verilator lint_off MULTIDRIVEN */
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reg [1:0] finish;
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/* verilator lint_on MULTIDRIVEN */
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reg sane;
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reg [128:0] cycles;
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always @(posedge reset)begin
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sane<=1;
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end
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always @(posedge clock) begin
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/* Allow some clock cycles for the waveform*/
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case(finish)
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2'd0: begin end
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2'd1: begin
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finish <= 2;
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/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
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$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
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`ifdef CALCULATE_IPC
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$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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instruction_count_temp <= instruction_count;
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`endif
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end
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2'd2: begin
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finish <= 3;
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`ifdef OUTPUT_JSON_STATISTICS
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if(json_file_descriptor!=0)
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$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
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`endif
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$finish;
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end
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2'd3: begin
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end
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endcase
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end
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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end
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endcase
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$display("Cycles run for: %0d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, system.sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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end
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always @(negedge clock)begin
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if(reset==1)
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cycles<=cycles+1;
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else begin
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cycles<=0;
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`ifdef OUTPUT_JSON_STATISTICS
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instruction_count <= 0;
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`endif
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end
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end
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`endif
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endmodule
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