(Tim) Efthimis Kritikos 2fcc521f12 Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!		2023-12-05 02:50:21 +00:00
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external_ip	Added .keep file for intentionally empty directory	2023-12-03 19:30:59 +00:00
fpga_config/OrangeCrab_r0.2.1	Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!	2023-12-05 02:50:21 +00:00
peripherals	Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!	2023-12-05 02:50:21 +00:00
alu_header.v	Added partial support for the software interrupt INT instruction	2023-03-08 07:26:28 +00:00
alu.v	More small fixes	2023-11-04 08:31:05 +00:00
biu.v	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00
boot_code.asm	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00
config.v	Peripherals/BuiltinRam: Fixed high impedance warning in yosys	2023-12-04 17:04:22 +00:00
decoder.v	Processor/Instructions: Fixed a bug where if IN executed after a microcoded instruction the cpu would go into undefined behavior	2023-11-26 00:18:15 +00:00
error_header.v	First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching	2023-05-07 13:34:15 +01:00
exec_state_def.v	Removed more "conflicting driver" issues with yet more performance penalties...	2023-11-04 15:33:23 +00:00
execute.v	Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space	2023-11-25 04:12:05 +00:00
general.v	Cleaned up some pieces of code and fixed a bug	2023-05-04 00:49:04 +01:00
Makefile	Build system: Added maximum CPU frequency to build system info and improved the way nextpnr seed is handled, fixing builds with older versions of make	2023-12-05 01:13:43 +00:00
memory.v	Peripherals/BuiltinRam: Fixed high impedance warning in yosys	2023-12-04 17:04:22 +00:00
processor.v	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00
registers.v	Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!	2023-11-15 18:43:56 +00:00
system.v	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00
testbench.cpp	Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation	2023-11-04 11:04:22 +00:00
testbench.v	Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space	2023-11-25 04:12:05 +00:00
ucode_header.v	Added partial support for the software interrupt INT instruction	2023-03-08 07:26:28 +00:00
ucode.txt	Changed slogan and cleaned up some small pieces of code	2023-05-23 16:18:33 +01:00
verilator_makefile	Removed erroneous file and run aspell	2023-03-21 14:51:39 +00:00