(Tim) Efthimis Kritikos 533f346f9b Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.		2023-12-07 16:39:04 +00:00
..
ascii_to_HD44780_driver.v	Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!	2023-11-15 18:43:56 +00:00
I2C_driver.v	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00
pcf8574_for_HD44780.v	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00
Wishbone_IO_driver.v	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00
Wishbone_memory_driver.v	Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.	2023-12-07 16:39:04 +00:00