150 lines
3.5 KiB
Verilog
150 lines
3.5 KiB
Verilog
/* Wishbone_driver.v - Implements a classic wishbone master that maps directly in memory space
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module Wishbone_memory_driver (
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input wire clock,
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input wire reset_n,
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input wire [19:0] address,
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input wire [15:0] data_bus_in,
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output reg [15:0] data_bus_out,
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output reg wait_state,
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input read_n,
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input write_n,
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input chip_select_n,
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input wire wb_mem_ack,
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output wire [24:0] wb_mem_adr,
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output wire wb_mem_cyc,
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/* verilator lint_off UNUSEDSIGNAL */
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// I don't yet use the upper word
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input wire [31:0] wb_mem_data_r,
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/* verilator lint_on UNUSEDSIGNAL */
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output wire [31:0] wb_mem_data_w,
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input wire wb_mem_err,
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output wire [3:0] wb_mem_sel,
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output wire wb_mem_stb,
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output wire wb_mem_we
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);
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reg WISHBONE_ACTIVE_CYCLE=1'b0;
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/* verilator lint_off UNUSEDSIGNAL */
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wire WISHBONE_ERROR_IN;
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/* verilator lint_on UNUSEDSIGNAL */
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reg [3:0]WISHBONE_SELECT=4'd0;
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reg WISHBONE_VALID_TRANSFER=1'b0;
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reg WISHBONE_WRITE=1'b1;
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wire WISHBONE_ACK_IN;
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reg [31:0]WISHBONE_DATA_READ=32'd0;
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wire [15:0]WISHBONE_DATA_WRITE;
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assign WISHBONE_ACK_IN=wb_mem_ack;
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assign wb_mem_adr={5'd0,address};
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assign WISHBONE_ERROR_IN=wb_mem_err;
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assign wb_mem_sel=WISHBONE_SELECT;
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assign wb_mem_stb=WISHBONE_VALID_TRANSFER;
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assign wb_mem_cyc=WISHBONE_ACTIVE_CYCLE;
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assign wb_mem_we=WISHBONE_WRITE;
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assign WISHBONE_DATA_WRITE=wb_mem_data_r[15:0];
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assign wb_mem_data_w=WISHBONE_DATA_READ;
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wire CYCLE_END=(WISHBONE_ACK_IN==1'b1);//||WISHBONE_ERROR_IN==1'b1);
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reg [3:0] state;
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always @(*) begin
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wait_state=0;
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if(reset_n==1) begin
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case(state)
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4'd0:begin
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if( chip_select_n && ((!read_n)||(!write_n)) )begin
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wait_state=1;
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end else begin
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wait_state=0;
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end
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end
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4'd1:begin
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wait_state=1;
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end
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4'd2:begin
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wait_state=1;
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end
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4'd3:begin
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wait_state=1;
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end
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4'd4:begin
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wait_state=0;
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end
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default:begin
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end
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endcase
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end else begin
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wait_state=0;
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end
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end
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always @(posedge clock)begin
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if(reset_n==0)
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state<=0;
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else begin
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case(state)
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4'd0:begin
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if( chip_select_n && ((!read_n)||(!write_n)) )begin
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state<=4'd1;
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end
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end
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4'd1:begin
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WISHBONE_ACTIVE_CYCLE<=1;
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WISHBONE_VALID_TRANSFER<=1;
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WISHBONE_SELECT<=4'hF;
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WISHBONE_WRITE<=read_n;
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if(read_n)begin
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state<=4'd2;
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WISHBONE_DATA_READ<={16'h0,data_bus_in};
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end else
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state<=4'd3;
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end
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4'd2:begin
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if(CYCLE_END==1'b1)begin
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state<=4'd4;
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WISHBONE_ACTIVE_CYCLE<=0;
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WISHBONE_VALID_TRANSFER<=0;
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end
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end
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4'd3:begin
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if(CYCLE_END==1'b1)begin
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data_bus_out<=WISHBONE_DATA_WRITE[15:0];
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state<=4'd4;
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WISHBONE_ACTIVE_CYCLE<=0;
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WISHBONE_VALID_TRANSFER<=0;
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end
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end
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4'd4:begin
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if(read_n&&write_n)
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state<=4'd0;
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end
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default:begin
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state<=4'd0;
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end
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endcase
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end
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end
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endmodule
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