101 lines
2.2 KiB
Verilog
101 lines
2.2 KiB
Verilog
/* top.v - Implements FPGA and Board specific circuitry
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "error_header.v"
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module fpga_top(
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input clk48,
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input user_button,
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// output reset_n,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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);
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wire HALT;
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wire [`ERROR_BITS-1:0]ERROR;
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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system system(
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/* MISC */ clk48,reset
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/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
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);
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reg [2:0]rgb_led_color;
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assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color=3'b000;
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else
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rgb_led_color=3'b111;
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end
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end
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// A bit useless since if the cpu ERORRS out or HALTS it will continue executing anyway
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//always @(HALT or ERROR or user_button) begin
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// if (HALT==1) begin
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// /* yellow */
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// rgb_led_color<=3'b100;
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// end else if (ERROR != `ERROR_BITS'b0) begin
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// /* red */
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// rgb_led_color<=3'b110;
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// end else begin
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// /* green */
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// rgb_led_color<=3'b101;
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// end
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//end
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/*** RESET CIRCUIT ***/
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reg [3:0] counter = 0;
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always @(posedge clk48) begin
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counter <= counter + 1;
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end
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reg reset=0;
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reg [1:0] state=0;
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always @(posedge counter[3]) begin
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if(user_button==0)
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state=2'b00;
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case (state)
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2'b00:begin
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reset<=0;
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state<=2'b01;
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end
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2'b01:begin
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reset<=1;
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state<=2'b10;
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end
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default: begin
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end
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endcase
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end
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endmodule
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