9086/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v

/* top.v - Implements FPGA and Board specific circuitry

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "error_header.v"

module fpga_top(
	input clk48,

	input user_button,
//	output reset_n,

	output rgb_led0_r,
	output rgb_led0_g,
	output rgb_led0_b,
);

wire HALT;
wire [`ERROR_BITS-1:0]ERROR;
wire [19:0] address_bus;
wire [15:0] data_bus_read,data_bus_write;
wire rd,wr,BHE,IOMEM;
system system(
	/*     MISC    */ clk48,reset
	/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
);

reg [2:0]rgb_led_color;
assign rgb_led0_r=rgb_led_color[0];
assign rgb_led0_g=rgb_led_color[1];
assign rgb_led0_b=rgb_led_color[2];

always @(negedge wr) begin
	if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
		if(data_bus_write[0:0]==1)
			rgb_led_color=3'b000;
		else
			rgb_led_color=3'b111;
	end
end

// A bit useless since if the cpu ERORRS out or HALTS it will continue executing anyway
//always @(HALT or ERROR or user_button) begin
//	if (HALT==1) begin
//		/* yellow */
//		rgb_led_color<=3'b100;
//	end else if (ERROR != `ERROR_BITS'b0) begin
//		/* red */
//		rgb_led_color<=3'b110;
//	end else begin
//		/* green */
//		rgb_led_color<=3'b101;
//	end
//end


/*** RESET CIRCUIT ***/

reg [3:0] counter = 0;

always @(posedge clk48) begin
    counter <= counter + 1;
end

reg reset=0;
reg [1:0] state=0;

always @(posedge counter[3]) begin
	if(user_button==0)
		state=2'b00;
	case (state)
		2'b00:begin
			reset<=0;
			state<=2'b01;
		end
		2'b01:begin
			reset<=1;
			state<=2'b10;
		end
		default: begin
		end
	endcase
end

endmodule