(Tim) Efthimis Kritikos
1966ab78b4
I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
119 lines
2.9 KiB
Verilog
119 lines
2.9 KiB
Verilog
/* I2C_driver_multiplexer.v - Implements a multiplexer for the SoC side of I2C_driver.v
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This file is part of the 9086 project.
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Copyright (c) 2024 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module I2C_driver_multiplexer (
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input wire clock,
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input wire reset_n,
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////// INPUT 1 ///////
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input wire [6:0] IN1_ADDRESS,
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output reg IN1_BUSY,
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input wire IN1_TRANSACT,
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input wire IN1_DIR,
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output reg [15:0] IN1_I2C_DATA_READ,
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input wire [15:0] IN1_I2C_DATA_WRITE,
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input IN1_TRANS_WIDTH,
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input IN1_IGN_ACK,
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////// INPUT 2 ///////
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input wire [6:0] IN2_ADDRESS,
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output reg IN2_BUSY,
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input wire IN2_TRANSACT,
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input wire IN2_DIR,
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output reg [15:0] IN2_I2C_DATA_READ,
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input wire [15:0] IN2_I2C_DATA_WRITE,
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input IN2_TRANS_WIDTH,
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input IN2_IGN_ACK,
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////// OUTPUT ///////
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output wire [6:0] OUT_ADDRESS,
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input wire OUT_BUSY,
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output reg OUT_TRANSACT,
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output wire OUT_DIR,
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input wire [15:0] OUT_I2C_DATA_READ,
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output wire [15:0] OUT_I2C_DATA_WRITE,
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output OUT_TRANS_WIDTH,
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output wire OUT_IGN_ACK
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);
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reg select;
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assign OUT_TRANS_WIDTH = select ? IN1_TRANS_WIDTH : IN2_TRANS_WIDTH;
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assign OUT_I2C_DATA_WRITE = select ? IN1_I2C_DATA_WRITE : IN2_I2C_DATA_WRITE;
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assign OUT_ADDRESS = select ? IN1_ADDRESS : IN2_ADDRESS;
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assign OUT_IGN_ACK = select ? IN1_IGN_ACK : IN2_IGN_ACK;
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assign OUT_DIR= select ? IN1_DIR : IN2_DIR;
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reg [1:0] STATE;
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reg SERVICED;
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always @(posedge clock)begin
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if(reset_n==1'b0)begin
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OUT_TRANSACT<=0;
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IN1_BUSY<=0;
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IN2_BUSY<=0;
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STATE<=2'd0;
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end else begin
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case(STATE)
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2'd0:begin
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if(IN1_TRANSACT&&OUT_BUSY==1'b0)begin
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select<=1'b1;
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OUT_TRANSACT<=1;
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STATE<=2'd1;
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SERVICED<=1'b0;
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end else if(IN2_TRANSACT&&OUT_BUSY==1'b0)begin
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select<=1'b0;
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OUT_TRANSACT<=1;
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IN1_BUSY<=1;
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STATE<=2'd1;
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SERVICED<=1'b1;
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end
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if(OUT_BUSY==1'b0)begin
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IN1_BUSY<=0;
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IN2_BUSY<=0;
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end
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end
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2'd1:begin
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if(OUT_BUSY==1'b1)begin
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STATE<=2'd0;
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OUT_TRANSACT<=0;
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end
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if(SERVICED==1'b0)begin
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IN1_BUSY<=1;
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end else begin
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IN2_BUSY<=1;
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end
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end
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default:begin
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STATE<=2'b0;
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end
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endcase
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end
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end
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always @(negedge OUT_BUSY)begin
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if(select)begin
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IN1_I2C_DATA_READ<=OUT_I2C_DATA_READ;
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end else begin
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IN2_I2C_DATA_READ<=OUT_I2C_DATA_READ;
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end
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end
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endmodule
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