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3 changed files with 4 additions and 38 deletions

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# 9086
A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
### Progress
* [X] Executing code
* [ ] can calculate the sieve of Eratosthenes
* [ ] can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [ ] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
### Building it
To build it you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils.
Go into the cpu directory and run `make`
At the time of development the versions used are :
* Icarus Verilog version 11.0 (stable)
* bin86 version: 0.16.17
* GNU Make 4.3
* xxd 2022-01-14
* GNU coreutils 8.32
An binary compatible 8086 CPU with as many optimizations as possible

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@ -14,22 +14,9 @@ wave: ${VVP}
vvp ${VVP} -lxt2
gtkwave test.lx2 gtkwave_savefile.gtkw
${VVP} : ${SOURCES} ${INCLUDES} boot_code.txt
${VVP} : ${SOURCES} ${INCLUDES}
iverilog -g2012 ${SOURCES} -o $@
.PHONY: clean
clean:
rm -f ${VVP} test.lx2 boot_code.txt boot_code.bin
boot_code.txt:boot_code.bin
dd if=/dev/zero bs=1 count=256 of=boot_code.stage status=none
dd if=boot_code.bin of=boot_code.stage conv=notrunc,nocreat status=none
xxd -ps -c 2 boot_code.stage > boot_code.txt
rm boot_code.stage
boot_code.bin:boot_code.asm
as86 -0 $< -b $@
.PHONY: dumpas
dumpas: boot_code.bin
objdump -D -b binary -m i8086 boot_code.bin
rm -f ${VVP} test.lx2

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module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
reg [15:0] memory [0:127];
reg [15:0] memory [0:15];
initial begin
$readmemh("boot_code.txt", memory);
end