8 lines
216 B
Verilog
8 lines
216 B
Verilog
module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
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reg [15:0] memory [0:15];
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initial begin
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$readmemh("boot_code.txt", memory);
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end
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assign data = !rd & !cs ? memory[address]: 'hz;
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endmodule
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