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| @ -48,13 +48,16 @@ Additionally, for ECP5 FPGAs: | |||||||
| * prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a ) | * prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a ) | ||||||
| * nextpnr : 0.6 | * nextpnr : 0.6 | ||||||
| 
 | 
 | ||||||
|  | Additionally, if you need a DRAM/DDR controller, the project supports litedram: | ||||||
|  | 
 | ||||||
|  | * Litedram : 2023.08 | ||||||
|  | * Migen : 0.9.2 | ||||||
|  | * Litex : 2023.08 | ||||||
|  | 
 | ||||||
| Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader | Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader | ||||||
| 
 | 
 | ||||||
| * dfu-util : 0.11 | * dfu-util : 0.11 | ||||||
| 
 | 
 | ||||||
| Additionally, if you need a DRAM/DDR controller, the project supports litedram but all the dependencies |  | ||||||
| needed to build it are downloaded automatically by the appropriate script. |  | ||||||
| 
 |  | ||||||
| ### High level design overview | ### High level design overview | ||||||
| 
 | 
 | ||||||
| <img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg"> | <img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg"> | ||||||
|  | |||||||
| @ -411,15 +411,14 @@ pcf8574_for_HD44780 PCF8574_driver( | |||||||
| 
 | 
 | ||||||
| // I2C driver | // I2C driver | ||||||
| 
 | 
 | ||||||
| wire SCL,SDA_input,SDA_output,SDA_direction,I2C_BUSY,I2C_SEND; | wire SCL,SDA,I2C_BUSY,I2C_SEND; | ||||||
| assign gpio_1=SCL; | assign gpio_1=SCL; | ||||||
|  | assign gpio_0=SDA; | ||||||
| 
 | 
 | ||||||
| I2C_driver i2c_driver( | I2C_driver i2c_driver( | ||||||
| 	.clock(I2C_SPEED), | 	.clock(I2C_SPEED), | ||||||
| 
 | 
 | ||||||
| 	.SDA_input(SDA_input), | 	.SDA_(SDA), | ||||||
| 	.SDA_output(SDA_output), |  | ||||||
| 	.SDA_direction(SDA_direction), |  | ||||||
| 	.SCL(SCL), | 	.SCL(SCL), | ||||||
| 
 | 
 | ||||||
| 	.address(7'h27), | 	.address(7'h27), | ||||||
| @ -428,19 +427,4 @@ I2C_driver i2c_driver( | |||||||
| 	.i2c_data(i2c_data) | 	.i2c_data(i2c_data) | ||||||
| ); | ); | ||||||
| 
 | 
 | ||||||
| TRELLIS_IO #( |  | ||||||
| 	// Parameters. |  | ||||||
| 	.DIR ("BIDIR") |  | ||||||
| ) TRELLIS_IO_00 ( |  | ||||||
| 	// pin |  | ||||||
| 	.B (gpio_0), |  | ||||||
| 	//input |  | ||||||
| 	.I (1'd0), |  | ||||||
| 	//Direction |  | ||||||
| 	.T (~( SDA_direction & (~SDA_output) )), |  | ||||||
| 	// Output |  | ||||||
| 	.O (SDA_input) |  | ||||||
| ); |  | ||||||
| 
 |  | ||||||
| 
 |  | ||||||
| endmodule | endmodule | ||||||
|  | |||||||
| @ -19,9 +19,7 @@ | |||||||
| 
 | 
 | ||||||
| module I2C_driver ( | module I2C_driver ( | ||||||
| 	input wire clock, | 	input wire clock, | ||||||
| 	input wire SDA_input, | 	inout wire SDA_, | ||||||
| 	output wire SDA_output, |  | ||||||
| 	output reg SDA_direction, //1:output 0:input |  | ||||||
| 	output reg SCL, | 	output reg SCL, | ||||||
| 
 | 
 | ||||||
| 	input wire [6:0] address, | 	input wire [6:0] address, | ||||||
| @ -32,7 +30,8 @@ module I2C_driver ( | |||||||
| 
 | 
 | ||||||
| reg SDA; | reg SDA; | ||||||
| 
 | 
 | ||||||
| assign SDA_output=SDA; | reg i2c_bus_dir=0; | ||||||
|  | assign SDA_=(i2c_bus_dir==0)?SDA:1'bz; | ||||||
| 
 | 
 | ||||||
| reg [5:0] i2c_state = 6'b100100; | reg [5:0] i2c_state = 6'b100100; | ||||||
| 
 | 
 | ||||||
| @ -44,7 +43,7 @@ always @(posedge clock) begin | |||||||
| 	case (i2c_state) | 	case (i2c_state) | ||||||
| 	/***** start sequence ******/ | 	/***** start sequence ******/ | ||||||
| 		6'b000000:begin | 		6'b000000:begin | ||||||
| 			SDA_direction<=1; | 			i2c_bus_dir<=0; | ||||||
| 			SDA<=1; | 			SDA<=1; | ||||||
| 			SCL<=1; | 			SCL<=1; | ||||||
| 			i2c_state<=6'b000001; | 			i2c_state<=6'b000001; | ||||||
| @ -104,7 +103,7 @@ always @(posedge clock) begin | |||||||
| 	/****** Acknowledge ********/ | 	/****** Acknowledge ********/ | ||||||
| 		6'b001011:begin | 		6'b001011:begin | ||||||
| 			SCL<=0; | 			SCL<=0; | ||||||
| 			SDA_direction<=0; | 			i2c_bus_dir<=1; | ||||||
| 			i2c_state<=6'b001100; | 			i2c_state<=6'b001100; | ||||||
| 		end | 		end | ||||||
| 		6'b001100:begin | 		6'b001100:begin | ||||||
| @ -153,7 +152,7 @@ always @(posedge clock) begin | |||||||
| 	/****** Send data ********/ | 	/****** Send data ********/ | ||||||
| 		6'b010100:begin | 		6'b010100:begin | ||||||
| 			SCL<=0; | 			SCL<=0; | ||||||
| 			SDA_direction<=1; | 			i2c_bus_dir<=0; | ||||||
| 			i2c_state<=6'b010101; | 			i2c_state<=6'b010101; | ||||||
| 		end | 		end | ||||||
| 		6'b010101:begin | 		6'b010101:begin | ||||||
| @ -176,7 +175,7 @@ always @(posedge clock) begin | |||||||
| 		end | 		end | ||||||
| 	/****** Acknowledge ********/ | 	/****** Acknowledge ********/ | ||||||
| 		6'b011000:begin | 		6'b011000:begin | ||||||
| 			SDA_direction<=0; | 			i2c_bus_dir<=1; | ||||||
| 			SCL<=0; | 			SCL<=0; | ||||||
| 			i2c_state<=6'b011001; | 			i2c_state<=6'b011001; | ||||||
| 		end | 		end | ||||||
| @ -195,7 +194,7 @@ always @(posedge clock) begin | |||||||
| 		//		i2c_state<=6'b011111; | 		//		i2c_state<=6'b011111; | ||||||
| 		//	end else begin | 		//	end else begin | ||||||
| 				i2c_state<=6'b011100; | 				i2c_state<=6'b011100; | ||||||
| 				SDA_direction<=1; | 				i2c_bus_dir<=0; | ||||||
| 		//	end | 		//	end | ||||||
| 		end | 		end | ||||||
| 	/****** separator ********/ | 	/****** separator ********/ | ||||||
|  | |||||||
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