|
|
fe0426a77b
|
Made execute unit run in parallel with everything else. Still not parallel for most of the time though
|
2023-05-13 06:51:35 +01:00 |
|
|
|
a8ab6b2dc7
|
Separated the execution unit from decode
|
2023-05-11 12:22:49 +01:00 |
|
|
|
da51dd6da7
|
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
|
2023-05-07 13:34:15 +01:00 |
|
|
|
11624ca2d2
|
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
|
2023-03-09 06:03:13 +00:00 |
|
|
|
99cbc49e95
|
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
|
2023-03-05 00:10:55 +00:00 |
|
|
|
7fde422341
|
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
|
2023-02-22 01:28:23 +00:00 |
|
|
|
ded47555a5
|
Improved build system and project directory structure
|
2023-02-16 01:52:02 +00:00 |
|
