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39f55aa6c3
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Added unaligned access for instructions and data and fixed register file access
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2023-02-10 12:02:20 +00:00 |
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185efe9d85
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Improved execution state logic, cleaned up code and fixed register file output enable
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2023-02-10 01:45:27 +00:00 |
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a5571fda12
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Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions!
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2023-02-09 20:17:15 +00:00 |
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f10d785f95
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Fixed dependency misconfiguration in Makefile
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2023-02-09 17:03:13 +00:00 |
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be31d74f74
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Fixed warning about standards compliance
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2023-02-09 14:55:24 +00:00 |
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a166efec9c
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Moved clock generator to the testbench
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2023-02-09 14:51:50 +00:00 |
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c3a2f5eb01
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Added primitive decode stage, improved state handling and fixed CIR register
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2023-02-09 14:46:21 +00:00 |
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76572a39ad
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Fix documentation
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2023-02-09 09:43:13 +00:00 |
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5371caa3bb
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Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
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2023-02-08 23:59:06 +00:00 |
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08bf5d3031
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Cleaned up and added opcode examples in the 8086 doc
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2023-02-08 23:04:55 +00:00 |
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eefea44673
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Removed erroneous backup file
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2023-02-08 20:55:49 +00:00 |
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361d98b7e6
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Added some documentation for the 8086 opcodes
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2023-02-08 20:52:17 +00:00 |
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139ec3c0c0
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Standardised indentation
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2023-02-08 12:09:21 +00:00 |
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61a403271c
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Added ROM, address and data buses and primitive program counter
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2023-02-08 11:57:22 +00:00 |
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bc2ef977d8
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Improved state logic
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2023-02-08 09:36:32 +00:00 |
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f9393cb69f
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Basic start for the control block
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2023-02-08 09:18:00 +00:00 |
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f94a0e9bb3
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Initial commit
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2023-02-08 08:38:10 +00:00 |
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