2 Commits

Author	SHA1	Message	Date
(Tim) Efthimis Kritikos	2fcc521f12	Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!	2023-12-05 02:50:21 +00:00
(Tim) Efthimis Kritikos	63ea29e399	Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)	2023-12-03 19:24:39 +00:00