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43f3e16ca4
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Removed all instances of inout since from what i understand it's mostly synthesisable
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2023-11-02 21:48:12 +00:00 |
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79d598fc64
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Changed slogan and cleaned up some small pieces of code
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2023-05-23 16:18:33 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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ba52ff89e6
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Fixed most problems verilator's linter found
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2023-03-04 06:22:28 +00:00 |
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f60084344e
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Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
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2023-03-03 06:29:06 +00:00 |
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6e8d951360
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Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
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2023-02-24 17:38:23 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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ed3d7101d3
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Further improved build system and changed brainfuck print message
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2023-02-16 23:26:32 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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