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be402aa8f7
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Project: updated copyright notices and README and fixed a few spelling mistakes
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2024-02-10 15:52:13 +00:00 |
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533f346f9b
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Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
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2023-12-07 16:39:04 +00:00 |
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2fcc521f12
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Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!
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2023-12-05 02:50:21 +00:00 |
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63ea29e399
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Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
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2023-12-03 19:24:39 +00:00 |
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