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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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e4ef199b83
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Fixed a memory corruption bug
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2023-05-10 08:35:14 +01:00 |
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f4b22951d0
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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11624ca2d2
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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f60084344e
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Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
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2023-03-03 06:29:06 +00:00 |
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6e8d951360
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Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
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2023-02-24 17:38:23 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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