|
|
43f3e16ca4
|
Removed all instances of inout since from what i understand it's mostly synthesisable
|
2023-11-02 21:48:12 +00:00 |
|
|
|
5feee9de57
|
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
|
2023-11-02 00:29:14 +00:00 |
|
|
|
e4ef199b83
|
Fixed a memory corruption bug
|
2023-05-10 08:35:14 +01:00 |
|
|
|
f4b22951d0
|
Cleaned up some pieces of code and fixed a bug
|
2023-05-04 00:49:04 +01:00 |
|
|
|
11624ca2d2
|
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
|
2023-03-09 06:03:13 +00:00 |
|
|
|
5705b8e8a5
|
Added support for Verilator!
|
2023-03-04 08:37:43 +00:00 |
|
|
|
f60084344e
|
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
|
2023-03-03 06:29:06 +00:00 |
|
|
|
6e8d951360
|
Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
|
2023-02-24 17:38:23 +00:00 |
|
|
|
fd4a9b5442
|
Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
|
2023-02-19 00:20:53 +00:00 |
|
|
|
ded47555a5
|
Improved build system and project directory structure
|
2023-02-16 01:52:02 +00:00 |
|
