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(Tim) Efthimis Kritikos
3e66336456
Build system: Small fixes and corrected rebuild when only the verilator testbench was changed
2023-12-09 02:39:14 +00:00
(Tim) Efthimis Kritikos
533f346f9b
Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
2023-12-07 16:39:04 +00:00