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Project: Fixed verilator warnings for fpga_sim

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This commit is contained in:
(Tim) Efthimis Kritikos 2024-02-26 13:12:26 +00:00
parent c527a053a6
commit fde181aa66
2 changed files with 8 additions and 2 deletions
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6
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
View File

@ -528,6 +528,10 @@ wire [15:0]MULT_TO_DRIV_DATA_WRITE, MULT_TO_DRIV_DATA_READ;
wire MULT_TO_DRIV_DIR;
wire CPU_I2C_TRANS_WIDTH;
/* verilator lint_off UNUSEDSIGNAL */
wire DISP_ERROR; //TODO: It would be ideal to acknoledge any warnings but it's not really too important
/* verilator lint_on UNUSEDSIGNAL */
I2C_driver_multiplexer I2C_driver_multiplexer(
.clock(I2C_SPEED),
.reset_n(reset),
@ -541,7 +545,7 @@ I2C_driver_multiplexer I2C_driver_multiplexer(
.IN1_I2C_DATA_WRITE({8'h0,DISP_I2C_DATA_WRITE}),
.IN1_TRANS_WIDTH(1'b0),
.IN1_IGN_ACK(1'b0),
//.IN2_ERROR(),
.IN1_ERROR(DISP_ERROR),
////// INPUT 2 ///////
.IN2_ADDRESS(CPU_I2C_OUT_ADDRESS),

4
system/peripherals/I2C_driver.v
View File

@ -30,10 +30,12 @@ module I2C_driver (
input wire DIR,
input wire [15:0] i2c_data_write,
input wire transact_width, /* 0=byte 1=word */
/* verilator lint_off UNUSEDSIGNAL */
input wire ignore_ack,
/* verilator lint_on UNUSEDSIGNAL */
output reg [15:0] i2c_data_read=16'h4141,
output reg error=0,
output reg error=0
);
//assign i2c_data_read=16'h0042;