Made the simulation stop at an unrecognised instruction or other error
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@ -11,7 +11,7 @@ assign out = (sel == 'b00) ? in1 :
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in4;
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endmodule
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
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/*** Global Definitions ***/
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// State
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@ -35,7 +35,6 @@ always @(negedge reset) begin
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@(posedge clock);
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state=`PROC_HALT_STATE;
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ProgCount=0;//TODO: Reset Vector
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EXCEPTION=0;
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HALT=0;
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reg_read=1;
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reg_write=1;
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@ -48,8 +47,6 @@ always @(negedge reset) begin
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end
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end
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reg EXCEPTION;
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/*** ALU and EXEC stage logic ***/
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//Architectural Register file
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@ -91,7 +88,7 @@ ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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/*** Processor stages ***/
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
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always @(negedge clock) begin
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case(state)
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@ -132,7 +129,7 @@ always @(posedge clock) begin
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`PROC_HALT_STATE:begin
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end
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`PROC_IF_STATE_ENTRY:begin
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EXCEPTION=0;
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ERROR=0;
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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@ -268,7 +265,7 @@ always @(posedge clock) begin
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`PROC_EX_STATE_ENTRY:begin
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reg_data=ADDER16_1O;
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state=`PROC_EX_STATE_EXIT;
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EXCEPTION=0;
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ERROR=0;
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end
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endcase
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end
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@ -7,8 +7,9 @@ reg clk_enable;
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wire [19:0]address_bus;
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wire [15:0]data_bus;
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wire rd,wr,romcs,HALT;
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wire ERROR;
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processor p(clock,reset,address_bus,data_bus,rd,wr,HALT);
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processor p(clock,reset,address_bus,data_bus,rd,wr,HALT,ERROR);
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rom bootrom(address_bus,data_bus,rd,romcs);
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`define CPU_SPEED 1000
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@ -36,6 +37,13 @@ always @(posedge HALT) begin
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$finish;
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end
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always @(posedge ERROR) begin
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$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
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$writememh("memdump.txt", bootrom.memory);
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#(`CPU_SPEED) //Just for the waveform
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$finish;
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end
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always @(posedge clock)begin
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if(reset==1)
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cycles=cycles+1;
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