From fd31eb704cc482f8b892d81df8f48edb21d04d48 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Sat, 11 Feb 2023 01:05:19 +0000
Subject: [PATCH] Made the simulation stop at an unrecognised instruction or
 other error

---
 cpu/processor.v | 11 ++++-------
 cpu/testbench.v | 10 +++++++++-
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/cpu/processor.v b/cpu/processor.v
index f51edbe..e96f7f3 100644
--- a/cpu/processor.v
+++ b/cpu/processor.v
@@ -11,7 +11,7 @@ assign out = (sel == 'b00) ? in1 :
 	in4;
 endmodule
 
-module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
+module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
 
 /*** Global Definitions ***/
 // State
@@ -35,7 +35,6 @@ always @(negedge reset) begin
 		@(posedge clock);
 		state=`PROC_HALT_STATE;
 		ProgCount=0;//TODO: Reset Vector
-		EXCEPTION=0;
 		HALT=0;
 		reg_read=1;
 		reg_write=1;
@@ -48,8 +47,6 @@ always @(negedge reset) begin
 	end
 end
 
-reg EXCEPTION;
-
 /*** ALU and EXEC stage logic ***/
 
 //Architectural Register file
@@ -91,7 +88,7 @@ ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
 
 /*** Processor stages ***/
 
-`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
+`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
 
 always @(negedge clock) begin
 	case(state)
@@ -132,7 +129,7 @@ always @(posedge clock) begin
 		`PROC_HALT_STATE:begin
 		end
 		`PROC_IF_STATE_ENTRY:begin
-			EXCEPTION=0;
+			ERROR=0;
 			external_address_bus <= ProgCount;
 			read <= 0;
 			write <= 1;
@@ -268,7 +265,7 @@ always @(posedge clock) begin
 		`PROC_EX_STATE_ENTRY:begin
 			reg_data=ADDER16_1O;
 			state=`PROC_EX_STATE_EXIT;
-			EXCEPTION=0;
+			ERROR=0;
 		end
 	endcase
 end
diff --git a/cpu/testbench.v b/cpu/testbench.v
index 2a955d0..19019ff 100644
--- a/cpu/testbench.v
+++ b/cpu/testbench.v
@@ -7,8 +7,9 @@ reg  clk_enable;
 wire [19:0]address_bus;
 wire [15:0]data_bus;
 wire rd,wr,romcs,HALT;
+wire ERROR;
 
-processor p(clock,reset,address_bus,data_bus,rd,wr,HALT);
+processor p(clock,reset,address_bus,data_bus,rd,wr,HALT,ERROR);
 rom bootrom(address_bus,data_bus,rd,romcs);
 
 `define CPU_SPEED 1000
@@ -36,6 +37,13 @@ always @(posedge HALT) begin
 	$finish;
 end
 
+always @(posedge ERROR) begin
+	$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
+	$writememh("memdump.txt", bootrom.memory);
+	#(`CPU_SPEED) //Just for the waveform
+	$finish;
+end
+
 always @(posedge clock)begin
 	if(reset==1)
 		cycles=cycles+1;