Efthimis/9086
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 1 Wiki Activity

Made the simulation stop at an unrecognised instruction or other error

Browse Source
This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-11 01:05:19 +00:00
parent fc4ecdb8d2
commit fd31eb704c
2 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
cpu/processor.v
View File

@ -11,7 +11,7 @@ assign out = (sel == 'b00) ? in1 :
in4; in4;
endmodule endmodule
module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT); module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
/*** Global Definitions ***/ /*** Global Definitions ***/
// State // State
@ -35,7 +35,6 @@ always @(negedge reset) begin
@(posedge clock); @(posedge clock);
state=`PROC_HALT_STATE; state=`PROC_HALT_STATE;
ProgCount=0;//TODO: Reset Vector ProgCount=0;//TODO: Reset Vector
EXCEPTION=0;
HALT=0; HALT=0;
reg_read=1; reg_read=1;
reg_write=1; reg_write=1;
@ -48,8 +47,6 @@ always @(negedge reset) begin
end end
end end
reg EXCEPTION;
/*** ALU and EXEC stage logic ***/ /*** ALU and EXEC stage logic ***/
//Architectural Register file //Architectural Register file
@ -91,7 +88,7 @@ ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
/*** Processor stages ***/ /*** Processor stages ***/
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1; `define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
always @(negedge clock) begin always @(negedge clock) begin
case(state) case(state)
@ -132,7 +129,7 @@ always @(posedge clock) begin
`PROC_HALT_STATE:begin `PROC_HALT_STATE:begin
end end
`PROC_IF_STATE_ENTRY:begin `PROC_IF_STATE_ENTRY:begin
EXCEPTION=0; ERROR=0;
external_address_bus <= ProgCount; external_address_bus <= ProgCount;
read <= 0; read <= 0;
write <= 1; write <= 1;
@ -268,7 +265,7 @@ always @(posedge clock) begin
`PROC_EX_STATE_ENTRY:begin `PROC_EX_STATE_ENTRY:begin
reg_data=ADDER16_1O; reg_data=ADDER16_1O;
state=`PROC_EX_STATE_EXIT; state=`PROC_EX_STATE_EXIT;
EXCEPTION=0; ERROR=0;
end end
endcase endcase
end end

10
cpu/testbench.v
View File

@ -7,8 +7,9 @@ reg clk_enable;
wire [19:0]address_bus; wire [19:0]address_bus;
wire [15:0]data_bus; wire [15:0]data_bus;
wire rd,wr,romcs,HALT; wire rd,wr,romcs,HALT;
wire ERROR;
processor p(clock,reset,address_bus,data_bus,rd,wr,HALT); processor p(clock,reset,address_bus,data_bus,rd,wr,HALT,ERROR);
rom bootrom(address_bus,data_bus,rd,romcs); rom bootrom(address_bus,data_bus,rd,romcs);
`define CPU_SPEED 1000 `define CPU_SPEED 1000
@ -36,6 +37,13 @@ always @(posedge HALT) begin
$finish; $finish;
end end
always @(posedge ERROR) begin
$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
$writememh("memdump.txt", bootrom.memory);
#(`CPU_SPEED) //Just for the waveform
$finish;
end
always @(posedge clock)begin always @(posedge clock)begin
if(reset==1) if(reset==1)
cycles=cycles+1; cycles=cycles+1;