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Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-25 04:11:51 +00:00
parent 17638d5cbd
commit f07e0e7c1f
6 changed files with 58 additions and 17 deletions
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19
system/boot_code.asm
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@ -25,16 +25,21 @@ dec [si]
dec cx
cmp CX,#0x00
MOV CH,#0x9A
TEST CH,#0x70
inw #0x20
CMP AL,#0xCD
jz WAZZ
mov ah,#2
mov dl,#'1
int #0x21
mov al,#'0
out byte #0xA5
hlt
WAZZ:
mov ah,#2
mov dl,#'0
int #0x21
CMP AH,#0xAB
jz WAZZ2
mov al,#'0
out byte #0xA5
hlt
WAZZ2:
mov al,#'1
outb #0xA5
hlt
TEST_:
ADD AX,#0xDEAD

25
system/decoder.v
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@ -822,6 +822,7 @@ always @( posedge clock ) begin
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction
MEM_OR_IO<=1;
ALU_OP<=`ALU_OP_ADD;
end
11'b1100_1111_???:begin
/* IRET - Return from interrupt */
@ -924,6 +925,27 @@ always @( posedge clock ) begin
`unimpl_addressing_mode
end
end
11'b1110_010?_???:begin
/* IN - Read from a defined port to AL or AX */
/* | 1 1 1 0 0 1 0 W | DATA 8 | */
memio_address_select=1;
OUT_MOD=3'b011;
Wbit=INSTRUCTION[24:24];
opcode_size=0;
in_alu_sel1=2'b00;
in_alu_sel2=2'b00;
PARAM2= {8'b0,INSTRUCTION[23:16]}; //TODO: this is a bit of a hack, i should've used PARAM_ACTION but it loads into PARAM1 and messes up my next_state
PARAM1<=0;
reg_write_addr<={Wbit,3'b000};
reg_read_port1_addr<={Wbit,3'b000};
DEPENDS_ON_PREVIOUS<=0;
IN_MOD=3'b110;
MEM_OR_IO<=1;
HALT<=0;
ERROR<=0;
ALU_OP<=`ALU_OP_ADD;
next_state=`EXEC_MEMIO_READ_SETADDR;
end
default:begin
`invalid_instruction
end
@ -1047,7 +1069,8 @@ module InstrSize ( input [10:0] IN, output reg [2:0] VERDICT );
11'b1010_100?_??? : VERDICT = 3'd2+{2'b0,IN[3:3]}; /* TEST - Bitwise AND affecting only flags */
11'b0000_00??_??? : VERDICT = 3'd2; /* ADD - Reg/memory with register to either */
11'b0010_10??_??? : VERDICT = 3'd2; /* SUB - Reg/memory with register to either */
11'b0011_10??_??? : VERDICT = 3'd2; /* CMP - Compare Register/memory and register */
11'b0011_10??_??? : VERDICT = 3'd2; /* CMP - Compare Register/memory and register */
11'b1110_010?_??? : VERDICT = 3'd2; /* IN - Read from a defined port to AL or AX */
default: VERDICT = 3'd7;
endcase
end

3
system/execute.v
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@ -196,6 +196,9 @@ always @(posedge clock) begin
endcase
end
`EXEC_MEMIO_READ_SETADDR:begin
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
if(memio_address_select==0)
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
else

2
system/processor.v
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@ -188,7 +188,7 @@ assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_r
wire [15:0] reg_read_port1_data, reg_read_port2_data;
register_file register_file(
/* WRITE */ .write_port1_addr(reg_write_addr),
/* WRITE */ .write_port1_addr(reg_write_addr), //TODO: should this come from exec instead?
/* */ .write_port1_data(ALU_O),
/* */ .write_port1_we(reg_write_we),
/* READ 1 */ .read_port1_addr(reg_read_port1_addr),

23
system/system.v
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@ -22,7 +22,7 @@
`include "config.v"
module system ( input clock,input reset, output [19:0]address_bus, input [15:0]data_bus_read, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
module system ( input clock,input reset, output [19:0]address_bus, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
`ifdef CALCULATE_IPC
wire new_instruction;
@ -33,14 +33,14 @@ wire unsigned [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT;
wire VALID_INSTRUCTION_STAT,jump_req;
`endif
wire [15:0]data_bus_read_,data_bus_write_;
wire [15:0]data_bus_read_CPU,data_bus_write_CPU;
assign data_bus_read_=data_bus_read;
assign data_bus_write=data_bus_write_;
assign data_bus_read_CPU=(IOMEM==0)?data_bus_read_RAM:data_bus_IO;
assign data_bus_write=data_bus_write_CPU;
processor p(
/* MISC */ clock,reset,HALT,ERROR
/* MEMORY / IO */ ,address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM
/* MEMORY / IO */ ,address_bus,data_bus_read_CPU,data_bus_write_CPU,rd,wr,BHE,IOMEM
`ifdef CALCULATE_IPC
/* STATISTICS */ ,new_instruction
`endif
@ -49,7 +49,9 @@ processor p(
`endif
);
doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM,clock);
wire [15:0] data_bus_read_RAM;
doublemem sysmem(address_bus,data_bus_read_RAM,data_bus_write_CPU,rd,wr,BHE,IOMEM,clock);
`ifdef OUTPUT_JSON_STATISTICS
string stats_name,version,commit;
@ -102,6 +104,8 @@ always @(negedge clock)begin
end
`endif
reg [15:0]data_bus_IO;
`ifndef SYNTHESIS
always @(negedge wr) begin
if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
@ -113,6 +117,13 @@ always @(negedge wr) begin
$display("\x1b[7mLed turned off\x1b[m\n");
end
end
always @(negedge rd) begin
if(IOMEM==1'b1 && address_bus[7:1]==7'h10 )begin // 0xABCD on address 0x20
data_bus_IO<=16'hABCD;
end else begin
data_bus_IO<=16'h0000;
end
end
`endif

3
system/testbench.v
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@ -25,7 +25,7 @@ wire clock;
reg reset;
reg clk_enable;
wire [19:0]address_bus;
wire [15:0]data_bus_read,data_bus_write;
wire [15:0]data_bus_write;
wire rd,wr,HALT;
wire [2:0] ERROR;
wire IOMEM;
@ -33,7 +33,6 @@ wire IOMEM;
system system( .clock(clock),
.reset(reset),
.address_bus(address_bus),
.data_bus_read(data_bus_read),
.data_bus_write(data_bus_write),
.rd(rd),
.wr(wr),