Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space
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@ -25,16 +25,21 @@ dec [si]
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dec cx
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cmp CX,#0x00
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MOV CH,#0x9A
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TEST CH,#0x70
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inw #0x20
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CMP AL,#0xCD
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jz WAZZ
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mov ah,#2
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mov dl,#'1
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int #0x21
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mov al,#'0
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out byte #0xA5
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hlt
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WAZZ:
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mov ah,#2
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mov dl,#'0
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int #0x21
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CMP AH,#0xAB
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jz WAZZ2
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mov al,#'0
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out byte #0xA5
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hlt
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WAZZ2:
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mov al,#'1
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outb #0xA5
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hlt
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TEST_:
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ADD AX,#0xDEAD
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@ -822,6 +822,7 @@ always @( posedge clock ) begin
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next_state=`EXEC_WRITE_ENTRY;
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`normal_instruction
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MEM_OR_IO<=1;
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ALU_OP<=`ALU_OP_ADD;
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end
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11'b1100_1111_???:begin
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/* IRET - Return from interrupt */
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@ -924,6 +925,27 @@ always @( posedge clock ) begin
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`unimpl_addressing_mode
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end
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end
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11'b1110_010?_???:begin
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/* IN - Read from a defined port to AL or AX */
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/* | 1 1 1 0 0 1 0 W | DATA 8 | */
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memio_address_select=1;
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OUT_MOD=3'b011;
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Wbit=INSTRUCTION[24:24];
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opcode_size=0;
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in_alu_sel1=2'b00;
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in_alu_sel2=2'b00;
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PARAM2= {8'b0,INSTRUCTION[23:16]}; //TODO: this is a bit of a hack, i should've used PARAM_ACTION but it loads into PARAM1 and messes up my next_state
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PARAM1<=0;
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reg_write_addr<={Wbit,3'b000};
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reg_read_port1_addr<={Wbit,3'b000};
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DEPENDS_ON_PREVIOUS<=0;
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IN_MOD=3'b110;
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MEM_OR_IO<=1;
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HALT<=0;
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ERROR<=0;
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ALU_OP<=`ALU_OP_ADD;
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next_state=`EXEC_MEMIO_READ_SETADDR;
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end
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default:begin
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`invalid_instruction
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end
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@ -1048,6 +1070,7 @@ module InstrSize ( input [10:0] IN, output reg [2:0] VERDICT );
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11'b0000_00??_??? : VERDICT = 3'd2; /* ADD - Reg/memory with register to either */
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11'b0010_10??_??? : VERDICT = 3'd2; /* SUB - Reg/memory with register to either */
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11'b0011_10??_??? : VERDICT = 3'd2; /* CMP - Compare Register/memory and register */
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11'b1110_010?_??? : VERDICT = 3'd2; /* IN - Read from a defined port to AL or AX */
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default: VERDICT = 3'd7;
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endcase
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end
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@ -196,6 +196,9 @@ always @(posedge clock) begin
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endcase
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end
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`EXEC_MEMIO_READ_SETADDR:begin
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/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
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/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
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if(memio_address_select==0)
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BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
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else
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@ -188,7 +188,7 @@ assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_r
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wire [15:0] reg_read_port1_data, reg_read_port2_data;
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register_file register_file(
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/* WRITE */ .write_port1_addr(reg_write_addr),
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/* WRITE */ .write_port1_addr(reg_write_addr), //TODO: should this come from exec instead?
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/* */ .write_port1_data(ALU_O),
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/* */ .write_port1_we(reg_write_we),
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/* READ 1 */ .read_port1_addr(reg_read_port1_addr),
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@ -22,7 +22,7 @@
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`include "config.v"
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module system ( input clock,input reset, output [19:0]address_bus, input [15:0]data_bus_read, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
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module system ( input clock,input reset, output [19:0]address_bus, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR);
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`ifdef CALCULATE_IPC
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wire new_instruction;
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@ -33,14 +33,14 @@ wire unsigned [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT;
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wire VALID_INSTRUCTION_STAT,jump_req;
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`endif
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wire [15:0]data_bus_read_,data_bus_write_;
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wire [15:0]data_bus_read_CPU,data_bus_write_CPU;
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assign data_bus_read_=data_bus_read;
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assign data_bus_write=data_bus_write_;
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assign data_bus_read_CPU=(IOMEM==0)?data_bus_read_RAM:data_bus_IO;
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assign data_bus_write=data_bus_write_CPU;
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processor p(
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/* MISC */ clock,reset,HALT,ERROR
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/* MEMORY / IO */ ,address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM
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/* MEMORY / IO */ ,address_bus,data_bus_read_CPU,data_bus_write_CPU,rd,wr,BHE,IOMEM
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,new_instruction
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`endif
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@ -49,7 +49,9 @@ processor p(
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`endif
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);
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doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM,clock);
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wire [15:0] data_bus_read_RAM;
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doublemem sysmem(address_bus,data_bus_read_RAM,data_bus_write_CPU,rd,wr,BHE,IOMEM,clock);
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`ifdef OUTPUT_JSON_STATISTICS
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string stats_name,version,commit;
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@ -102,6 +104,8 @@ always @(negedge clock)begin
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end
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`endif
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reg [15:0]data_bus_IO;
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`ifndef SYNTHESIS
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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@ -113,6 +117,13 @@ always @(negedge wr) begin
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$display("\x1b[7mLed turned off\x1b[m\n");
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end
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end
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always @(negedge rd) begin
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if(IOMEM==1'b1 && address_bus[7:1]==7'h10 )begin // 0xABCD on address 0x20
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data_bus_IO<=16'hABCD;
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end else begin
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data_bus_IO<=16'h0000;
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end
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end
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`endif
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@ -25,7 +25,7 @@ wire clock;
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reg reset;
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reg clk_enable;
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wire [19:0]address_bus;
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wire [15:0]data_bus_read,data_bus_write;
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wire [15:0]data_bus_write;
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wire rd,wr,HALT;
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wire [2:0] ERROR;
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wire IOMEM;
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@ -33,7 +33,6 @@ wire IOMEM;
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system system( .clock(clock),
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.reset(reset),
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.address_bus(address_bus),
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.data_bus_read(data_bus_read),
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.data_bus_write(data_bus_write),
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.rd(rd),
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.wr(wr),
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