Efthimis/9086
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Run the project through aspell and tweaked the README

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(Tim) Efthimis Kritikos 2023-02-19 00:52:52 +00:00
parent fd4a9b5442
commit e6c9c722e3
5 changed files with 9 additions and 9 deletions
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2
8086_documentation.md
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@ -45,7 +45,7 @@ Example instructions:
| Bytecode | AT&T Syntax | meaning | | Bytecode | AT&T Syntax | meaning |
| ---------- | --------------- | ---------------------------------------------------------- | | ---------- | --------------- | ---------------------------------------------------------- |
|81 c0 aa 55 | add $0x55aa,%ax | add 0x55aa to register ax | |81 c0 aa 55 | add $0x55aa,%ax | add 0x55aa to register ax |
|03 06 aa 55 | add 0x55aa,%ax | add the contents of memory locaton 0x55aa to register ax | |03 06 aa 55 | add 0x55aa,%ax | add the contents of memory location 0x55aa to register ax |
|fe c0 | inc %al | increment register al | |fe c0 | inc %al | increment register al |
|ff c0 | inc %ax | increment register ax | |ff c0 | inc %ax | increment register ax |
|40 | inc %ax | increment register ax | |40 | inc %ax | increment register ax |

8
README.md
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@ -1,6 +1,5 @@
<img width="186" height="70" align="left" style="float: left; margin: 0 10px 0 0;" alt="9086 logo" src="readme_files/9086_design1.svg"> <img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
#
A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible
@ -13,8 +12,9 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
* [ ] Is Out of Order * [ ] Is Out of Order
* [ ] Is superscalar * [ ] Is superscalar
### Building it ### Simulating it
To build this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils and run `make` on the top level directory. To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils.
After that you can run `make` on the top level directory and it should build everything and start the simulation
At the time of development the versions used are : At the time of development the versions used are :

2
boot_code/brainfuck_interpreter_v0.asm
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@ -124,6 +124,6 @@ JMP INTERPRET
PROG_END: PROG_END:
hlt hlt
bootup_msg: .ASCII 'Brainfuck interpeter v0\n' bootup_msg: .ASCII 'Brainfuck interpreter v0\n'
bracket: .BLKB 280 bracket: .BLKB 280
data: .BLKB 560 data: .BLKB 560

4
system/decoder.v
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@ -381,7 +381,7 @@ always @( CIR ) begin
`invalid_instruction `invalid_instruction
end end
2'b01: begin 2'b01: begin
/* JMP - Uncoditional Jump direct within segment */ /* JMP - Unconditional Jump direct within segment */
/* 1 1 1 0 1 0 0 1 | IP-INC-LO | IP-INC-HI |*/ /* 1 1 1 0 1 0 0 1 | IP-INC-LO | IP-INC-HI |*/
`invalid_instruction `invalid_instruction
end end
@ -413,7 +413,7 @@ always @( CIR ) begin
end end
2'b01:begin 2'b01:begin
if(CIR[7:0]==8'h21) begin if(CIR[7:0]==8'h21) begin
/* INT - execut interrupt handler */ /* INT - execute interrupt handler */
/* 1 1 0 0 1 1 0 1 | DATA |*/ /* 1 1 0 0 1 1 0 1 | DATA |*/
has_operands=1; has_operands=1;
opcode_size=0; opcode_size=0;

2
system/processor.v
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@ -297,7 +297,7 @@ always @(posedge clock) begin
* word of the instruction which contains no useful * word of the instruction which contains no useful
* data anymore but the ProgCount has the correct * data anymore but the ProgCount has the correct
* address so update it now so that whatever the case * address so update it now so that whatever the case
* external_data_bus contains at leat some unkown data */ * external_data_bus contains at least some unknown data */
one_byte_instruction=(!has_operands)&&(!opcode_size); one_byte_instruction=(!has_operands)&&(!opcode_size);
external_address_bus = ProgCount; external_address_bus = ProgCount;
state=next_state; state=next_state;