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Improved instruction decoding

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(Tim) Efthimis Kritikos 2023-02-10 14:39:34 +00:00
parent 6561018206
commit e685c52ddd
1 changed files with 9 additions and 7 deletions
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16
cpu/processor.v
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@ -89,6 +89,9 @@ reg [15:0] temp_out;
ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C); ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
/*** Processor stages ***/ /*** Processor stages ***/
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
always @(negedge clock) begin always @(negedge clock) begin
case(state) case(state)
`PROC_IF_WRITE_CIR:begin `PROC_IF_WRITE_CIR:begin
@ -107,13 +110,14 @@ always @(negedge clock) begin
end end
`PROC_EX_STATE_EXIT:begin `PROC_EX_STATE_EXIT:begin
case(out_sel) case(out_sel)
2'b01:begin 2'b11:begin
reg_write=0; reg_write=0;
state=`PROC_IF_STATE_ENTRY;
end end
default:begin default:begin
`invalid_instruction
end end
endcase endcase
state=`PROC_IF_STATE_ENTRY;
end end
`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin `PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
external_address_bus = ProgCount; external_address_bus = ProgCount;
@ -122,8 +126,6 @@ always @(negedge clock) begin
endcase endcase
end end
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
always @(posedge clock) begin always @(posedge clock) begin
case(state) case(state)
`PROC_HALT_STATE: `PROC_HALT_STATE:
@ -151,7 +153,7 @@ always @(posedge clock) begin
unaligned_access=~unaligned_access; unaligned_access=~unaligned_access;
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=2'b01; out_sel=2'b11;
reg_read_addr=3'b000; reg_read_addr=3'b000;
reg_addr=3'b000; reg_addr=3'b000;
reg_read_read=0; reg_read_read=0;
@ -172,7 +174,7 @@ always @(posedge clock) begin
end end
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=2'b01; out_sel=CIR[7:6];
reg_read_addr=CIR[2:0]; reg_read_addr=CIR[2:0];
reg_addr=CIR[2:0]; reg_addr=CIR[2:0];
reg_read_read=0; reg_read_read=0;
@ -196,7 +198,7 @@ always @(posedge clock) begin
end end
in1_sel=2'b00; in1_sel=2'b00;
in2_sel=2'b01; in2_sel=2'b01;
out_sel=2'b01; out_sel=CIR[7:6];
PARAM1=1; PARAM1=1;
reg_read_addr=CIR[2:0]; reg_read_addr=CIR[2:0];
reg_addr=CIR[2:0]; reg_addr=CIR[2:0];