From e685c52ddd0099fa204182c0e962bcd90117ed9e Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Fri, 10 Feb 2023 14:39:34 +0000 Subject: [PATCH] Improved instruction decoding --- cpu/processor.v | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/cpu/processor.v b/cpu/processor.v index 23351ec..64defe5 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -89,6 +89,9 @@ reg [15:0] temp_out; ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C); /*** Processor stages ***/ + +`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1; + always @(negedge clock) begin case(state) `PROC_IF_WRITE_CIR:begin @@ -107,13 +110,14 @@ always @(negedge clock) begin end `PROC_EX_STATE_EXIT:begin case(out_sel) - 2'b01:begin + 2'b11:begin reg_write=0; + state=`PROC_IF_STATE_ENTRY; end default:begin + `invalid_instruction end endcase - state=`PROC_IF_STATE_ENTRY; end `PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin external_address_bus = ProgCount; @@ -122,8 +126,6 @@ always @(negedge clock) begin endcase end -`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1; - always @(posedge clock) begin case(state) `PROC_HALT_STATE: @@ -151,7 +153,7 @@ always @(posedge clock) begin unaligned_access=~unaligned_access; in1_sel=2'b00; in2_sel=2'b01; - out_sel=2'b01; + out_sel=2'b11; reg_read_addr=3'b000; reg_addr=3'b000; reg_read_read=0; @@ -172,7 +174,7 @@ always @(posedge clock) begin end in1_sel=2'b00; in2_sel=2'b01; - out_sel=2'b01; + out_sel=CIR[7:6]; reg_read_addr=CIR[2:0]; reg_addr=CIR[2:0]; reg_read_read=0; @@ -196,7 +198,7 @@ always @(posedge clock) begin end in1_sel=2'b00; in2_sel=2'b01; - out_sel=2'b01; + out_sel=CIR[7:6]; PARAM1=1; reg_read_addr=CIR[2:0]; reg_addr=CIR[2:0];