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Move the diagram below some text since it looks a bit ugly this way

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(Tim) Efthimis Kritikos 2023-11-07 14:40:51 +00:00
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@ -16,10 +16,6 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
* [X] Has been successfully synthesized * [X] Has been successfully synthesized
* [ ] Has a comprehensive testing framework * [ ] Has a comprehensive testing framework
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### Simulating it ### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk). Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
This list shows the software needed and the versions used during development : This list shows the software needed and the versions used during development :
@ -56,6 +52,10 @@ Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bo
* dfu-util : 0.11 * dfu-util : 0.11
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### License and Copyright ### License and Copyright
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later