From e0dc7bae073a9a9da8ec68cfbc8c8d6655f95314 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Tue, 7 Nov 2023 14:40:51 +0000
Subject: [PATCH] Move the diagram below some text since it looks a bit ugly
 this way

---
 README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 9c45bd3..ba1f1f9 100644
--- a/README.md
+++ b/README.md
@@ -16,10 +16,6 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
   * [X] Has been successfully synthesized
   * [ ] Has a comprehensive testing framework
 
-### High level design overview
-
-<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
-
 ### Simulating it
 Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
 This list shows the software needed and the versions used during development :
@@ -56,6 +52,10 @@ Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bo
 
 * dfu-util : 0.11
 
+### High level design overview
+
+<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
+
 ### License and Copyright
 All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later