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Slight adjustment to README

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(Tim) Efthimis Kritikos 2023-03-06 21:57:36 +00:00
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@ -15,13 +15,13 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
### Simulating it ### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog version 11.0 (stable) OR **(preferred)** Verilator 5.006 * Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.006
* bin86 : 0.16.21 * bin86 : 0.16.21
* GNU Make : 4.4.1 * GNU Make : 4.4.1
* xxd : 2022-01-14 * xxd : 2022-01-14
* GNU coreutils : 9.1 * POSIX coreutils : GNU coreutils 9.1
After that you can run `make` on the top level directory and it should build everything and start the simulation After that you can run `make` on the top level directory and it should build everything and start the simulation