From d93c92c00572d812c76d1b42969741d8cfce8d4d Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Mon, 6 Mar 2023 21:57:36 +0000 Subject: [PATCH] Slight adjustment to README --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index af45e12..4c9c327 100644 --- a/README.md +++ b/README.md @@ -15,13 +15,13 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat ### Simulating it Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) -Specifically this list shows the software needed and the versions used during development +Specifically this list shows the software needed and the versions used during development (other versions should work as well) -* Icarus Verilog version 11.0 (stable) OR **(preferred)** Verilator 5.006 +* Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.006 * bin86 : 0.16.21 * GNU Make : 4.4.1 * xxd : 2022-01-14 -* GNU coreutils : 9.1 +* POSIX coreutils : GNU coreutils 9.1 After that you can run `make` on the top level directory and it should build everything and start the simulation