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Finished MOV Reg/Mem to/from register

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(Tim) Efthimis Kritikos 2023-02-14 15:49:29 +00:00
parent f97f4625e6
commit c3563457c5
1 changed files with 24 additions and 11 deletions
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35
cpu/processor.v
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@ -160,7 +160,7 @@ always @(negedge clock) begin
state=`PROC_DE_STATE_ENTRY; state=`PROC_DE_STATE_ENTRY;
end end
`PROC_EX_STATE_EXIT:begin `PROC_EX_STATE_EXIT:begin
case(out_sel) case(out_sel) /*TODO: use RM*/
3'b000, 3'b000,
3'b001, 3'b001,
3'b010 : begin 3'b010 : begin
@ -376,30 +376,43 @@ always @(posedge clock) begin
MOD=CIR[7:6]; MOD=CIR[7:6];
RM=CIR[2:0]; RM=CIR[2:0];
Wbit=CIR[8:8]; Wbit=CIR[8:8];
if(CIR[9:9] == 1)begin
/* to reg */
MOD=CIR[7:6]; MOD=CIR[7:6];
in2_sel=2'b00;
if(CIR[9:9] == 1)begin
/* Mem/Reg to reg */
if(MOD==2'b11)begin if(MOD==2'b11)begin
/*Reg to Reg*/
in1_sel=2'b01; in1_sel=2'b01;
reg_read_addr=CIR[2:0]; reg_read_addr=CIR[2:0];
state=`PROC_EX_STATE_ENTRY;
reg_read_oe=0;
end else begin end else begin
/*Mem to Reg*/
in1_sel=2'b00; in1_sel=2'b00;
state=`RPOC_MEMIO_READ;
end end
in2_sel=2'b00;
out_sel=3'b011; out_sel=3'b011;
reg_write_addr={CIR[8:8],CIR[5:3]}; reg_write_addr={Wbit,CIR[5:3]};
end else begin end else begin
`invalid_instruction /* Reg to Mem/Reg */
if(MOD==2'b11)begin
/*Reg to Reg*/
out_sel=3'b011;
reg_write_addr={Wbit,CIR[2:0]};
state=`PROC_EX_STATE_ENTRY;
end else begin
/*Reg to Mem*/
out_sel={1'b0,RM};
state=`PROC_MEMIO_WRITE;
end
reg_read_oe=0;
in1_sel=2'b01;
reg_read_addr={Wbit,CIR[5:3]};
end end
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
PARAM2=0; PARAM2=0;
state=`PROC_DE_LOAD_16_PARAM;
if ( MOD == 2'b11 )
state=`PROC_EX_STATE_ENTRY;
else
state=`RPOC_MEMIO_READ;
end end
6'b010000,//INC 6'b010000,//INC
6'b010001,//INC 6'b010001,//INC