From c3563457c52f510b5f85d75b9844fac685fe799e Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Tue, 14 Feb 2023 15:49:29 +0000
Subject: [PATCH] Finished MOV Reg/Mem to/from register

---
 cpu/processor.v | 35 ++++++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/cpu/processor.v b/cpu/processor.v
index 96f8a98..9453ca2 100644
--- a/cpu/processor.v
+++ b/cpu/processor.v
@@ -160,7 +160,7 @@ always @(negedge clock) begin
 			state=`PROC_DE_STATE_ENTRY;
 		end
 		`PROC_EX_STATE_EXIT:begin
-			case(out_sel)
+			case(out_sel) /*TODO: use RM*/
 				3'b000,
 					3'b001,
 					3'b010 : begin
@@ -376,30 +376,43 @@ always @(posedge clock) begin
 					MOD=CIR[7:6];
 					RM=CIR[2:0];
 					Wbit=CIR[8:8];
+					MOD=CIR[7:6];
+					in2_sel=2'b00;
 					if(CIR[9:9] == 1)begin
-						/* to reg */
-						MOD=CIR[7:6];
+						/* Mem/Reg to reg */
 						if(MOD==2'b11)begin
+							/*Reg to Reg*/
 							in1_sel=2'b01;
 							reg_read_addr=CIR[2:0];
+							state=`PROC_EX_STATE_ENTRY;
+							reg_read_oe=0;
 						end else begin
+							/*Mem to Reg*/
 							in1_sel=2'b00;
+							state=`RPOC_MEMIO_READ;
 						end
-						in2_sel=2'b00;
 						out_sel=3'b011;
-						reg_write_addr={CIR[8:8],CIR[5:3]};
+						reg_write_addr={Wbit,CIR[5:3]};
 					end else begin
-						`invalid_instruction
+						/* Reg to Mem/Reg */
+						if(MOD==2'b11)begin
+							/*Reg to Reg*/
+							out_sel=3'b011;
+							reg_write_addr={Wbit,CIR[2:0]};
+							state=`PROC_EX_STATE_ENTRY;
+						end else begin
+							/*Reg to Mem*/
+							out_sel={1'b0,RM};
+							state=`PROC_MEMIO_WRITE;
+						end
+						reg_read_oe=0;
+						in1_sel=2'b01;
+						reg_read_addr={Wbit,CIR[5:3]};
 					end
 
 					ALU_1OE=0;
 					ALU_1OP=`ALU_OP_ADD;
 					PARAM2=0;
-					state=`PROC_DE_LOAD_16_PARAM;
-					if ( MOD == 2'b11 )
-						state=`PROC_EX_STATE_ENTRY;
-					else
-						state=`RPOC_MEMIO_READ;
 				end
 				6'b010000,//INC
 				6'b010001,//INC