Cleaned up the interface between BIU and the processor
This commit is contained in:
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07d2a80b2e
commit
bfa576e2a0
@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
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[*] Sat May 13 08:57:35 2023
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[*] Tue May 16 11:05:44 2023
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[*]
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[dumpfile] "/home/user/9086/system/boot_code.fst"
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[dumpfile_mtime] "Sat May 13 08:57:31 2023"
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[dumpfile_size] 13788
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[dumpfile_mtime] "Tue May 16 11:04:39 2023"
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[dumpfile_size] 7259
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[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
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[timestart] 87160000000
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[size] 1140 993
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[timestart] 33090000000
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[size] 1428 1003
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[pos] -1 -1
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*-31.895050 93500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-32.795048 62150000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.system.
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[treeopen] TOP.system.p.
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@ -19,41 +19,45 @@
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[sst_width] 263
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[signals_width] 231
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[sst_expanded] 1
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[sst_vpaned_height] 296
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@29
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[sst_vpaned_height] 298
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@28
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TOP.system.clock
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TOP.system.reset
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@23
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@22
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TOP.system.address_bus[19:0]
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TOP.system.data_bus[15:0]
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@29
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@28
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TOP.system.p.read
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TOP.system.p.write
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@201
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@200
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-
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@29
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@28
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TOP.system.p.BIU.VALID_INSTRUCTION
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@29
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TOP.system.p.valid_instruction_ack
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@28
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TOP.system.p.valid_exec_data
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@23
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@22
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TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
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TOP.system.p.BIU.biu_state[3:0]
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@29
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@28
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.proc_state[2:0]
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TOP.system.p.execute_unit.work
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TOP.system.p.BIU.write_request
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TOP.system.p.BIU.read_request
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TOP.system.p.SIMPLE_MICRO
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@23
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@22
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TOP.system.p.ucode_seq_addr[4:0]
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@29
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@28
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TOP.system.p.execute_unit.biu_jump_req
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@201
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@200
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-
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@29
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@28
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TOP.system.p.ERROR[2:0]
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TOP.system.IOMEM
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TOP.system.p.HALT
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@23
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@22
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TOP.system.p.BIU.INSTRUCTION[31:0]
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TOP.system.p.decoder.seq_addr_entry[4:0]
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TOP.system.p.BIU.FIFO_end[3:0]
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30
system/biu.v
30
system/biu.v
@ -42,7 +42,7 @@ module BIU (
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/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
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/* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req,
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/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
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/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO
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/* */ input valid_instruction_ack
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`ifdef OTUPUT_JSON_STATISTICS
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/* Statistics */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
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`endif
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@ -278,7 +278,6 @@ always @(posedge clock) begin
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VALID_INSTRUCTION <= 0;
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VALID_DATA <= 0;
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DATA_DIR <= 0;
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was_dec <= 0;
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end
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default: begin
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biu_state <= `BIU_NEXT_ACTION;/*Should be unreachable*/
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@ -297,37 +296,12 @@ InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+4'd1]
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Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
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`endif
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reg was_dec;
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reg was_simple;
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always @( proc_state ) begin
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case (proc_state)
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`PROC_DE_STATE_ENTRY: begin
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was_dec<=1;
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end
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default: begin
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if( SIMPLE_MICRO==0 && was_dec==1 )begin
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was_dec<=0;
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always @( valid_instruction_ack ) begin
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/* verilator lint_off BLKSEQ */
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FIFO_start = FIFO_start + {1'b0,Isize};
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
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VALID_INSTRUCTION <= 0;
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end else if ( SIMPLE_MICRO==1 && was_simple == 1) begin
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was_simple<=0;
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was_dec<=0;
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/* verilator lint_off BLKSEQ */
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FIFO_start = FIFO_start + {1'b0,Isize};
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
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VALID_INSTRUCTION <= 0;
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end
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end
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endcase
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end
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always @( negedge SIMPLE_MICRO ) begin
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was_simple <= 1;
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end
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always @( posedge jump_req ) begin
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@ -45,3 +45,5 @@
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`define EXEC_NEXT_MICROCODE 4'b1010
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`define EXEC_RESET 4'b1011
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`define EXEC_JUMP_RELEASE 4'b1101
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@ -108,7 +108,6 @@ always @(posedge clock) begin
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end
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`EXEC_DONE:begin
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reg_write_we <= 1;
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biu_jump_req <= 0;
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use_exec_reg_addr <= 0;
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if(valid_input)begin
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exec_state <= init_state;
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@ -311,8 +310,8 @@ always @(posedge clock) begin
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3'b101:begin /* Program Counter*/
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BIU_ADDRESS_INPUT <= ALU_O[15:0];
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biu_jump_req <= 1;
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exec_state <= `EXEC_DONE;
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work <= 0;
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exec_state <= `EXEC_JUMP_RELEASE;
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work <= 1;
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end
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3'b110:begin /* SP Indirect write*/
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reg_read_port1_addr <= 4'b1100;
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@ -331,6 +330,11 @@ always @(posedge clock) begin
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end
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endcase
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end
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`EXEC_JUMP_RELEASE:begin
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biu_jump_req <= 0;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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`EXEC_MEMIO_WRITE:begin
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/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
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/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
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@ -50,7 +50,7 @@ module processor (
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/* If there is an error either from the decoder or execution unit set it to ERROR */
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assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;
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reg [`PROC_STATE_BITS-1:0] state;
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reg [`PROC_STATE_BITS-1:0] proc_state;
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/*############ Execution Unit ################################################### */
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@ -101,13 +101,14 @@ wire [15:0] BIU_DATA;
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wire [31:0] INSTRUCTION;
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wire biu_write_request, biu_read_request, BIU_VALID_DATA;
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wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION;
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reg valid_instruction_ack;
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BIU BIU(
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/* Outside world */ clock,reset,external_address_bus
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/* */ ,external_data_bus,read,write,BHE,IOMEM
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/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
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/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
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/* */ ,state,SIMPLE_MICRO
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/* */ ,valid_instruction_ack
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`ifdef OTUPUT_JSON_STATISTICS
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/* Statistics */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
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`endif
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@ -187,13 +188,13 @@ register_file register_file(
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/*** RESET LOGIC ***/
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always @(negedge reset) begin
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state <= `PROC_HALT; //TODO: race condition ??
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proc_state <= `PROC_HALT; //TODO: race condition ??
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`ifdef CALCULATE_IPC
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new_instruction<=0;
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`endif
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end
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always @(posedge reset) begin
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state <= `PROC_RESET;
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proc_state <= `PROC_RESET;
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end
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/*** Processor stages ***/
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@ -206,13 +207,14 @@ reg [23:0] INSTRUCTION_BUFFER;
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reg owe_set_init;
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always @(posedge clock) begin
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case(state)
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case(proc_state)
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`PROC_RESET:begin
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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DE_OUTPUT_sampled <= 0;
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SIMPLE_MICRO <= 0;
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state <= `PROC_DE_STATE_ENTRY;
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owe_set_init<=0;
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proc_state <= `PROC_DE_STATE_ENTRY;
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owe_set_init <= 0;
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valid_instruction_ack <= 0;
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end
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`PROC_DE_STATE_ENTRY:begin
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if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin
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@ -220,6 +222,7 @@ always @(posedge clock) begin
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DE_OUTPUT_sampled <= DE_OUTPUT;
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if(SIMPLE_MICRO==0||owe_set_init==1)begin
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valid_instruction_ack <= !valid_instruction_ack;
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owe_set_init<=0;
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set_initial_values<=0;
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@ -236,10 +239,10 @@ always @(posedge clock) begin
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/*switch to microcode decoding*/
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
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end else begin
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valid_exec_data <= 1;
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state <= `PROC_WAIT;
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proc_state <= `PROC_WAIT;
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end
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end else begin
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if( DE_DEPENDS_ON_PREVIOUS == 0)
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@ -248,7 +251,7 @@ always @(posedge clock) begin
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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owe_set_init <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
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end
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end
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end
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@ -256,7 +259,7 @@ always @(posedge clock) begin
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`PROC_WAIT:begin
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set_initial_values<=1;
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valid_exec_data<=0;
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state <= `PROC_DE_STATE_ENTRY;
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proc_state <= `PROC_DE_STATE_ENTRY;
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if( SIMPLE_MICRO == 1 ) begin
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ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
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if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
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