From bfa576e2a0b22d93f4563a0deb28ab9800f237ea Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Tue, 16 May 2023 13:33:08 +0100 Subject: [PATCH] Cleaned up the interface between BIU and the processor --- gtkwave_savefile.gtkw | 42 ++++++++++++++++++++++------------------- system/biu.v | 40 +++++++-------------------------------- system/exec_state_def.v | 2 ++ system/execute.v | 10 +++++++--- system/processor.v | 25 +++++++++++++----------- 5 files changed, 53 insertions(+), 66 deletions(-) diff --git a/gtkwave_savefile.gtkw b/gtkwave_savefile.gtkw index ee3cd41..b629c9d 100644 --- a/gtkwave_savefile.gtkw +++ b/gtkwave_savefile.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI -[*] Sat May 13 08:57:35 2023 +[*] Tue May 16 11:05:44 2023 [*] [dumpfile] "/home/user/9086/system/boot_code.fst" -[dumpfile_mtime] "Sat May 13 08:57:31 2023" -[dumpfile_size] 13788 +[dumpfile_mtime] "Tue May 16 11:04:39 2023" +[dumpfile_size] 7259 [savefile] "/home/user/9086/gtkwave_savefile.gtkw" -[timestart] 87160000000 -[size] 1140 993 +[timestart] 33090000000 +[size] 1428 1003 [pos] -1 -1 -*-31.895050 93500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-32.795048 62150000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.system. [treeopen] TOP.system.p. @@ -19,41 +19,45 @@ [sst_width] 263 [signals_width] 231 [sst_expanded] 1 -[sst_vpaned_height] 296 -@29 +[sst_vpaned_height] 298 +@28 TOP.system.clock TOP.system.reset -@23 +@22 TOP.system.address_bus[19:0] TOP.system.data_bus[15:0] -@29 +@28 TOP.system.p.read TOP.system.p.write -@201 +@200 - -@29 +@28 TOP.system.p.BIU.VALID_INSTRUCTION +@29 +TOP.system.p.valid_instruction_ack +@28 TOP.system.p.valid_exec_data -@23 +@22 TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0] TOP.system.p.BIU.biu_state[3:0] -@29 +@28 TOP.system.p.execute_unit.exec_state[3:0] +TOP.system.p.proc_state[2:0] TOP.system.p.execute_unit.work TOP.system.p.BIU.write_request TOP.system.p.BIU.read_request TOP.system.p.SIMPLE_MICRO -@23 +@22 TOP.system.p.ucode_seq_addr[4:0] -@29 +@28 TOP.system.p.execute_unit.biu_jump_req -@201 +@200 - -@29 +@28 TOP.system.p.ERROR[2:0] TOP.system.IOMEM TOP.system.p.HALT -@23 +@22 TOP.system.p.BIU.INSTRUCTION[31:0] TOP.system.p.decoder.seq_addr_entry[4:0] TOP.system.p.BIU.FIFO_end[3:0] diff --git a/system/biu.v b/system/biu.v index 7e6c5e3..a50b4b3 100644 --- a/system/biu.v +++ b/system/biu.v @@ -42,7 +42,7 @@ module BIU ( /* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM, /* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req, /* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO, -/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO +/* */ input valid_instruction_ack `ifdef OTUPUT_JSON_STATISTICS /* Statistics */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT `endif @@ -278,7 +278,6 @@ always @(posedge clock) begin VALID_INSTRUCTION <= 0; VALID_DATA <= 0; DATA_DIR <= 0; - was_dec <= 0; end default: begin biu_state <= `BIU_NEXT_ACTION;/*Should be unreachable*/ @@ -297,37 +296,12 @@ InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+4'd1] Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1); `endif -reg was_dec; -reg was_simple; - -always @( proc_state ) begin - case (proc_state) - `PROC_DE_STATE_ENTRY: begin - was_dec<=1; - end - default: begin - if( SIMPLE_MICRO==0 && was_dec==1 )begin - was_dec<=0; - /* verilator lint_off BLKSEQ */ - FIFO_start = FIFO_start + {1'b0,Isize}; - /* verilator lint_on BLKSEQ */ - INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};; - VALID_INSTRUCTION <= 0; - end else if ( SIMPLE_MICRO==1 && was_simple == 1) begin - was_simple<=0; - was_dec<=0; - /* verilator lint_off BLKSEQ */ - FIFO_start = FIFO_start + {1'b0,Isize}; - /* verilator lint_on BLKSEQ */ - INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};; - VALID_INSTRUCTION <= 0; - end - end - endcase -end - -always @( negedge SIMPLE_MICRO ) begin - was_simple <= 1; +always @( valid_instruction_ack ) begin + /* verilator lint_off BLKSEQ */ + FIFO_start = FIFO_start + {1'b0,Isize}; + /* verilator lint_on BLKSEQ */ + INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};; + VALID_INSTRUCTION <= 0; end always @( posedge jump_req ) begin diff --git a/system/exec_state_def.v b/system/exec_state_def.v index 97d9d2b..10d4ba1 100644 --- a/system/exec_state_def.v +++ b/system/exec_state_def.v @@ -45,3 +45,5 @@ `define EXEC_NEXT_MICROCODE 4'b1010 `define EXEC_RESET 4'b1011 + +`define EXEC_JUMP_RELEASE 4'b1101 diff --git a/system/execute.v b/system/execute.v index 1519774..fe5ae96 100644 --- a/system/execute.v +++ b/system/execute.v @@ -108,7 +108,6 @@ always @(posedge clock) begin end `EXEC_DONE:begin reg_write_we <= 1; - biu_jump_req <= 0; use_exec_reg_addr <= 0; if(valid_input)begin exec_state <= init_state; @@ -311,8 +310,8 @@ always @(posedge clock) begin 3'b101:begin /* Program Counter*/ BIU_ADDRESS_INPUT <= ALU_O[15:0]; biu_jump_req <= 1; - exec_state <= `EXEC_DONE; - work <= 0; + exec_state <= `EXEC_JUMP_RELEASE; + work <= 1; end 3'b110:begin /* SP Indirect write*/ reg_read_port1_addr <= 4'b1100; @@ -331,6 +330,11 @@ always @(posedge clock) begin end endcase end + `EXEC_JUMP_RELEASE:begin + biu_jump_req <= 0; + exec_state <= `EXEC_DONE; + work <= 0; + end `EXEC_MEMIO_WRITE:begin /* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */ /* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */ diff --git a/system/processor.v b/system/processor.v index 5c16933..3bb99c0 100644 --- a/system/processor.v +++ b/system/processor.v @@ -50,7 +50,7 @@ module processor ( /* If there is an error either from the decoder or execution unit set it to ERROR */ assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR; -reg [`PROC_STATE_BITS-1:0] state; +reg [`PROC_STATE_BITS-1:0] proc_state; /*############ Execution Unit ################################################### */ @@ -101,13 +101,14 @@ wire [15:0] BIU_DATA; wire [31:0] INSTRUCTION; wire biu_write_request, biu_read_request, BIU_VALID_DATA; wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION; +reg valid_instruction_ack; BIU BIU( /* Outside world */ clock,reset,external_address_bus /* */ ,external_data_bus,read,write,BHE,IOMEM /* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req /* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO - /* */ ,state,SIMPLE_MICRO + /* */ ,valid_instruction_ack `ifdef OTUPUT_JSON_STATISTICS /* Statistics */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT `endif @@ -187,13 +188,13 @@ register_file register_file( /*** RESET LOGIC ***/ always @(negedge reset) begin - state <= `PROC_HALT; //TODO: race condition ?? + proc_state <= `PROC_HALT; //TODO: race condition ?? `ifdef CALCULATE_IPC new_instruction<=0; `endif end always @(posedge reset) begin - state <= `PROC_RESET; + proc_state <= `PROC_RESET; end /*** Processor stages ***/ @@ -206,13 +207,14 @@ reg [23:0] INSTRUCTION_BUFFER; reg owe_set_init; always @(posedge clock) begin - case(state) + case(proc_state) `PROC_RESET:begin ucode_seq_addr <= `UCODE_NO_INSTRUCTION; DE_OUTPUT_sampled <= 0; SIMPLE_MICRO <= 0; - state <= `PROC_DE_STATE_ENTRY; - owe_set_init<=0; + proc_state <= `PROC_DE_STATE_ENTRY; + owe_set_init <= 0; + valid_instruction_ack <= 0; end `PROC_DE_STATE_ENTRY:begin if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin @@ -220,6 +222,7 @@ always @(posedge clock) begin DE_OUTPUT_sampled <= DE_OUTPUT; if(SIMPLE_MICRO==0||owe_set_init==1)begin + valid_instruction_ack <= !valid_instruction_ack; owe_set_init<=0; set_initial_values<=0; @@ -236,10 +239,10 @@ always @(posedge clock) begin /*switch to microcode decoding*/ ucode_seq_addr <= ucode_seq_addr_entry; SIMPLE_MICRO <= 1; - /*keep state the same and rerun decode this time with all the data from the microcode rom*/ + /*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/ end else begin valid_exec_data <= 1; - state <= `PROC_WAIT; + proc_state <= `PROC_WAIT; end end else begin if( DE_DEPENDS_ON_PREVIOUS == 0) @@ -248,7 +251,7 @@ always @(posedge clock) begin ucode_seq_addr <= ucode_seq_addr_entry; SIMPLE_MICRO <= 1; owe_set_init <= 1; - /*keep state the same and rerun decode this time with all the data from the microcode rom*/ + /*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/ end end end @@ -256,7 +259,7 @@ always @(posedge clock) begin `PROC_WAIT:begin set_initial_values<=1; valid_exec_data<=0; - state <= `PROC_DE_STATE_ENTRY; + proc_state <= `PROC_DE_STATE_ENTRY; if( SIMPLE_MICRO == 1 ) begin ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/ if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin