Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
This commit is contained in:
parent
e0dc7bae07
commit
a88c420ca5
@ -69,10 +69,12 @@ endif
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ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
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ECP5_TARGETS+=abc.history # created from yosys
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EXTRA_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v
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#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
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synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} ../boot_code/colored_led.txt
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synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${INCLUDES} ../boot_code/colored_led.txt
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${QUIET_YOSYS}
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${Q} yosys -q -D BUILTIN_RAM=512 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ; synth_ecp5 -json $@"
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${Q} yosys -q -D BUILTIN_RAM=512 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ; synth_ecp5 -json $@ -top fpga_top"
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synth_ecp5_out.config:synth_ecp5.json
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${QUIET_NEXTPNR}
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@ -28,6 +28,9 @@ module fpga_top(
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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inout gpio_0,/*sda*/
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output gpio_1 /*scl*/
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);
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wire HALT;
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@ -35,6 +38,7 @@ wire [`ERROR_BITS-1:0]ERROR;
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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system system(
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/* MISC */ clk48,reset
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/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
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@ -45,15 +49,6 @@ assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color=3'b000;
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else
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rgb_led_color=3'b111;
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end
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end
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// A bit useless since if the cpu ERORRS out or HALTS it will continue executing anyway
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//always @(HALT or ERROR or user_button) begin
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// if (HALT==1) begin
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@ -68,15 +63,16 @@ end
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// end
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//end
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// Create a 27 bit register
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reg [26:0] counter = 0;
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/*** RESET CIRCUIT ***/
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reg [3:0] counter = 0;
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// Every positive edge increment register by 1
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always @(posedge clk48) begin
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counter <= counter + 1;
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end
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/*** RESET CIRCUIT ***/
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reg reset=0;
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reg [1:0] state=0;
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@ -97,4 +93,113 @@ always @(posedge counter[3]) begin
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endcase
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end
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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//disp_write_cache[disp_cache_end]<=data_bus_write[7:0];
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disp_write_cache[disp_cache_end]<=data_bus_write[15:8];
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disp_cache_end<=disp_cache_end+5'd1;
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color=3'b000;
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else
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rgb_led_color=3'b111;
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end
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end
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//------------------------------------------//
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// Cache to allow the slow display to have a
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// chance to keep up with the relentless CPU
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reg [4:0] disp_cache_start=0;
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reg [4:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [31:0];
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reg ascii_state=0;
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always @(posedge clk48)begin
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case (ascii_state)
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1'b0:begin
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if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
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ascii_data<=disp_write_cache[disp_cache_start];
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disp_cache_start<=disp_cache_start+5'd1;
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ascii_data_write_req<=1;
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ascii_state<=1'b1;
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end
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end
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1'b1:begin
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if(!ascii_data_ready)begin
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ascii_data_write_req<=0;
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ascii_state<=1'b0;
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end
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end
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default: begin end
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endcase
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end
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wire I2C_SPEED=counter[7];
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// Display driver
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wire ascii_data_ready;
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reg ascii_data_write_req=0;
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reg [7:0] ascii_data;
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ascii_to_HD44780_driver LCD_DRIVER(
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/* system */
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I2C_SPEED,
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1'b1,
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/* Data Input */
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ascii_data_ready,
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ascii_data_write_req,
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ascii_data,
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/* write circuitry */
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!pcf_busy,
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pcf_write_req,
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pcf_data,
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pcf_command_data
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);
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// Port expander driver
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wire pcf_write_req,pcf_command_data,pcf_busy;
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wire [3:0]pcf_data;
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wire [7:0]i2c_data;
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pcf8574_for_HD44780 PCF8574_driver(
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.clock(I2C_SPEED),
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.pcf_write_req(pcf_write_req),
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.pcf_command_data(pcf_command_data),
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.pcf_data(pcf_data),
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.pcf_busy(pcf_busy),
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.new_backlight(1'b0),
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.backlight_update(1'b0),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data)
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);
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// I2C driver
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wire SCL,SDA,I2C_BUSY,I2C_SEND;
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assign gpio_1=SCL;
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assign gpio_0=SDA;
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reg [7:0]i2c_data;
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I2C_driver i2c_driver(
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.clock(I2C_SPEED),
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.SDA_(SDA),
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.SCL(SCL),
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.address(7'h27),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data),
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);
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endmodule
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258
system/peripherals/I2C_driver.v
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258
system/peripherals/I2C_driver.v
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@ -0,0 +1,258 @@
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/* I2C_driver.v - Implements an I2C interface
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module I2C_driver (
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input wire clock,
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inout wire SDA_,
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output reg SCL,
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input wire [6:0] address,
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output reg I2C_BUSY=0,
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input wire I2C_SEND,
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input wire [7:0] i2c_data
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);
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reg SDA;
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assign SDA_=(i2c_bus_dir==0)?SDA:1'bz;
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reg i2c_bus_dir=0;
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reg [5:0] i2c_state = 6'b100100;
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reg [3:0] data_bit_counter;
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reg [7:0] data_internal;
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reg [6:0]address_internal;
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always @(posedge clock) begin
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case (i2c_state)
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/***** start sequence ******/
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6'b000000:begin
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i2c_bus_dir<=0;
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SDA<=1;
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SCL<=1;
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i2c_state<=6'b000001;
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end
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6'b000001:begin
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SDA<=0;
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SCL<=1;
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i2c_state<=6'b000010;
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end
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6'b000010:begin
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SDA<=0;
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SCL<=0;
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i2c_state<=6'b000011;
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data_bit_counter<=0;
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end
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/****** Set address ********/
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6'b000011:begin
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SCL<=0;
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i2c_state<=6'b000100;
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end
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6'b000100:begin
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SCL<=0;
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SDA<=address_internal[6:6];
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address_internal[6:0]<={address_internal[5:0],1'b0};
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b000101;
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end
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6'b000101:begin
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SCL<=1;
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i2c_state<=6'b000110;
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end
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6'b000110:begin
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SCL<=1;
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if(data_bit_counter==4'd7)
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i2c_state<=6'b000111;
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else
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i2c_state<=6'b000011;
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end
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/****** Read/Write *********/
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6'b000111:begin
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SCL<=0;
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i2c_state<=6'b001000;
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end
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6'b001000:begin
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SCL<=0;
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SDA<=0;/*Write=0 Read=1*/
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i2c_state<=6'b001001;
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end
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6'b001001:begin
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SCL<=1;
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i2c_state<=6'b001010;
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end
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6'b001010:begin
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SCL<=1;
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i2c_state<=6'b001011;
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end
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/****** Acknowledge ********/
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6'b001011:begin
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SCL<=0;
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i2c_bus_dir<=1;
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i2c_state<=6'b001100;
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end
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6'b001100:begin
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SCL<=0;
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i2c_state<=6'b001101;
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end
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6'b001101:begin
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SCL<=1;
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i2c_state<=6'b001110;
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end
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6'b001110:begin
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SCL<=1;
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// if (SDA==1)begin
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// led<=1;
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// i2c_state<=6'b011111;
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// end else begin
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i2c_state<=6'b001111;
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data_bit_counter<=0;
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// end
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end
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/****** separator ********/
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6'b001111:begin
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SCL<=0;
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SDA<=0;
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i2c_state<=6'b010000;
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end
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6'b010000:begin
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SCL<=0;
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i2c_state<=6'b010001;
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end
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6'b010001:begin
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SCL<=0;
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SDA<=1;
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i2c_state<=6'b010010;
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end
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6'b010010:begin
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SCL<=0;
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SDA<=1;
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i2c_state<=6'b010011;
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end
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6'b010011:begin
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SCL<=0;
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SDA<=0;
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i2c_state<=6'b010100;
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end
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/****** Send data ********/
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6'b010100:begin
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SCL<=0;
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i2c_bus_dir<=0;
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i2c_state<=6'b010101;
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end
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6'b010101:begin
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SCL<=0;
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SDA<=data_internal[7:7];
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data_internal[7:0]<={data_internal[6:0],1'b0};
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data_bit_counter<=data_bit_counter+1;
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i2c_state<=6'b010110;
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end
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6'b010110:begin
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SCL<=1;
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i2c_state<=6'b010111;
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end
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6'b010111:begin
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SCL<=1;
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if(data_bit_counter==4'd8)begin
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i2c_state<=6'b011000;
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end else
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i2c_state<=6'b010100;
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end
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/****** Acknowledge ********/
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6'b011000:begin
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i2c_bus_dir<=1;
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SCL<=0;
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i2c_state<=6'b011001;
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end
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6'b011001:begin
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SCL<=0;
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i2c_state<=6'b011010;
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end
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6'b011010:begin
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SCL<=1;
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i2c_state<=6'b011011;
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end
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6'b011011:begin
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SCL<=1;
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// if (SDA==1)begin
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// led<=1;
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// i2c_state<=6'b011111;
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// end else begin
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i2c_state<=6'b011100;
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i2c_bus_dir<=0;
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// end
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end
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/****** separator ********/
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6'b011100:begin
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SCL<=0;
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SDA<=0;
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i2c_state<=6'b011101;
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end
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6'b011101:begin
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SCL<=0;
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i2c_state<=6'b011110;
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end
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6'b011110:begin
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SCL<=0;
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SDA<=1;
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i2c_state<=6'b011111;
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end
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6'b011111:begin
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SCL<=0;
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SDA<=1;
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i2c_state<=6'b100000;
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end
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6'b100000:begin
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SCL<=0;
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SDA<=0;
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i2c_state<=6'b100001;
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end
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/****** stop bit *******/
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6'b100001:begin
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SCL<=1;
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SDA<=0;
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i2c_state<=6'b100010;
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end
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6'b100010:begin
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SCL<=1;
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SDA<=1;
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i2c_state<=6'b100011;
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end
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6'b100011:begin
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SCL<=1;
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SDA<=1;
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i2c_state<=6'b100100;
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I2C_BUSY<=0;
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end
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6'b100100:begin
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if(I2C_SEND==1)begin
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I2C_BUSY<=1;
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i2c_state<=0;
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data_internal<=i2c_data;
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address_internal<=address;
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end
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end
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default:begin
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SCL<=0;
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SDA<=0;
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end
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endcase
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end
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endmodule
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114
system/peripherals/ascii_to_HD44780_driver.v
Normal file
114
system/peripherals/ascii_to_HD44780_driver.v
Normal file
@ -0,0 +1,114 @@
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/* ascii_to_HD44780_driver.v - driver that takes in ascii and outputs control
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sequences for an HD44780 display
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|
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This file is part of the 9086 project.
|
||||
|
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Copyright (c) 2023 Efthymios Kritikos
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
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module ascii_to_HD44780_driver (
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/* system */
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input wire clock,
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input wire rst_n,
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/* Data Input */
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output reg in_data_ready=0,
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input data_write_req,
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input [7:0] in_ascii_data,
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/* write circuitry */
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input wire done_writing,
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output reg write_req=0,
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output reg [3:0] data,
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output reg cmd_data=0
|
||||
);
|
||||
|
||||
initial begin
|
||||
init_cmd_data[ 0] = 4'h3;
|
||||
init_cmd_data[ 1] = 4'h3;
|
||||
init_cmd_data[ 2] = 4'h3;
|
||||
init_cmd_data[ 3] = 4'h2;
|
||||
init_cmd_data[ 4] = 4'h2; //0x28
|
||||
init_cmd_data[ 5] = 4'h8;
|
||||
init_cmd_data[ 6] = 4'h0; //0x07
|
||||
init_cmd_data[ 7] = 4'h7;
|
||||
init_cmd_data[ 8] = 4'h0; //0x0C
|
||||
init_cmd_data[ 9] = 4'hC;
|
||||
init_cmd_data[10] = 4'h0; //0x01
|
||||
init_cmd_data[11] = 4'h1;
|
||||
init_cmd_data[12] = 4'h0; //0x06
|
||||
init_cmd_data[13] = 4'h6;
|
||||
init_cmd_data[14] = 4'h0; // 0x02
|
||||
init_cmd_data[15] = 4'h2;
|
||||
end
|
||||
|
||||
reg [4:0] init_seq=0;
|
||||
reg [5:0] data_write_wait_counter = 0;
|
||||
|
||||
reg [3:0] init_cmd_data [15:0];
|
||||
|
||||
reg byte_n=0;
|
||||
|
||||
reg data_write_latch=0;
|
||||
reg [7:0]print_data;
|
||||
|
||||
always @(posedge clock,negedge rst_n) begin
|
||||
if(rst_n==0)begin
|
||||
in_data_ready<=0;
|
||||
write_req<=1'b0;
|
||||
init_seq<=5'd0;
|
||||
data_write_wait_counter<=6'd0;
|
||||
byte_n<=1'b0;
|
||||
cmd_data<=1'b0;
|
||||
end else if(done_writing)begin
|
||||
if(init_seq!=5'd16&&data_write_wait_counter==6'd0)begin
|
||||
data<=init_cmd_data[init_seq[3:0]];
|
||||
init_seq<=init_seq+5'd1;
|
||||
write_req<=1'b1;
|
||||
data_write_wait_counter<=6'd50;
|
||||
in_data_ready<=0;
|
||||
end else if (data_write_wait_counter!=6'd0) begin
|
||||
data_write_wait_counter<=data_write_wait_counter-6'd1;
|
||||
write_req<=1'b0;
|
||||
in_data_ready<=0;
|
||||
end else if(data_write_req==1&&data_write_latch==0)begin
|
||||
data_write_latch<=1;
|
||||
print_data<=in_ascii_data;
|
||||
in_data_ready<=0;
|
||||
byte_n<=0;
|
||||
end else if(data_write_latch&byte_n==0)begin
|
||||
data<=print_data[7:4];
|
||||
write_req<=1'b1;
|
||||
data_write_wait_counter<=6'd50;
|
||||
byte_n<=1;
|
||||
end else if(data_write_latch&byte_n==1)begin
|
||||
data<=print_data[3:0];
|
||||
write_req<=1'b1;
|
||||
data_write_wait_counter<=6'd50;
|
||||
byte_n<=0;
|
||||
data_write_latch<=0;
|
||||
end else begin
|
||||
cmd_data<=1;
|
||||
in_data_ready<=1;
|
||||
end
|
||||
end else begin
|
||||
write_req<=1'b0;
|
||||
in_data_ready<=0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
123
system/peripherals/pcf8574_for_HD44780.v
Normal file
123
system/peripherals/pcf8574_for_HD44780.v
Normal file
@ -0,0 +1,123 @@
|
||||
/* pcf8574_for_HD44780.v - takes in control sequences for an HD44780 display
|
||||
and outputs data that control a pcf8574 connected to a HD44780 in a standard
|
||||
manner over i2c
|
||||
|
||||
This file is part of the 9086 project.
|
||||
|
||||
Copyright (c) 2023 Efthymios Kritikos
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
module pcf8574_for_HD44780(
|
||||
input wire clock,
|
||||
|
||||
input wire pcf_write_req,
|
||||
input wire pcf_command_data,
|
||||
input wire [3:0]pcf_data,
|
||||
output reg pcf_busy=0,
|
||||
input new_backlight,
|
||||
input backlight_update,
|
||||
|
||||
input I2C_BUSY,
|
||||
output reg I2C_SEND=0,
|
||||
|
||||
output reg [7:0]i2c_data
|
||||
);
|
||||
|
||||
reg backlight=1;
|
||||
reg backlight_latch=0;
|
||||
reg [3:0]pcf_state=0;
|
||||
|
||||
always @(posedge clock) begin
|
||||
// [ D7 , D6 , D5 , D4 , BACKLIGHT , EN , WRITE , COMMAND/DATA ]
|
||||
if(backlight_update)
|
||||
backlight_latch<=1;
|
||||
case(pcf_state)
|
||||
4'b0000: begin /*Idle*/
|
||||
if(pcf_write_req&&I2C_BUSY==0)begin
|
||||
pcf_state<=4'b0001;
|
||||
I2C_SEND<=0;
|
||||
pcf_busy<=1;
|
||||
end else if(backlight_latch&&I2C_BUSY==0)begin
|
||||
pcf_state<=4'b1111;
|
||||
I2C_SEND<=0;
|
||||
pcf_busy<=1;
|
||||
end
|
||||
end
|
||||
4'b0001: begin
|
||||
if(I2C_BUSY==0)begin
|
||||
i2c_data<={pcf_data[3:0],backlight,1'b0,1'b0,pcf_command_data};
|
||||
I2C_SEND<=1;
|
||||
backlight_latch<=0;
|
||||
pcf_state<=4'b0010;
|
||||
end
|
||||
end
|
||||
4'b0010:begin
|
||||
if(I2C_BUSY==1)begin
|
||||
I2C_SEND<=0;
|
||||
pcf_state<=4'b0011;
|
||||
end
|
||||
end
|
||||
4'b0011: begin
|
||||
if(I2C_BUSY==0)begin
|
||||
i2c_data<={pcf_data[3:0],backlight,1'b1,1'b0,pcf_command_data};
|
||||
I2C_SEND<=1;
|
||||
backlight_latch<=0;
|
||||
pcf_state<=4'b0100;
|
||||
end
|
||||
end
|
||||
4'b0100:begin
|
||||
if(I2C_BUSY==1)begin
|
||||
I2C_SEND<=0;
|
||||
pcf_state<=4'b0101;
|
||||
end
|
||||
end
|
||||
4'b0101: begin
|
||||
if(I2C_BUSY==0)begin
|
||||
i2c_data<={pcf_data[3:0],backlight,1'b0,1'b0,pcf_command_data};
|
||||
I2C_SEND<=1;
|
||||
pcf_state<=4'b0110;
|
||||
end
|
||||
end
|
||||
4'b0110: begin
|
||||
if(I2C_BUSY==1)begin
|
||||
I2C_SEND<=0;
|
||||
pcf_state<=4'b0111;
|
||||
end
|
||||
end
|
||||
4'b0111:begin
|
||||
if(I2C_BUSY==0)begin
|
||||
pcf_state<=4'b0000;
|
||||
pcf_busy<=1'b0;
|
||||
end
|
||||
end
|
||||
4'b1111:begin
|
||||
if(I2C_BUSY==1)begin
|
||||
pcf_state<=4'b0000;
|
||||
I2C_SEND<=1'b0;
|
||||
pcf_busy<=1'b0;
|
||||
end else begin
|
||||
i2c_data<={4'b0,backlight,1'b0,1'b0,1'b0};
|
||||
backlight_latch<=0;
|
||||
I2C_SEND<=1'b1;
|
||||
pcf_busy<=1'b1;
|
||||
end
|
||||
end
|
||||
default:begin
|
||||
pcf_state<=0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user