115 lines
2.9 KiB
Verilog
115 lines
2.9 KiB
Verilog
/* ascii_to_HD44780_driver.v - driver that takes in ascii and outputs control
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sequences for an HD44780 display
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module ascii_to_HD44780_driver (
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/* system */
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input wire clock,
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input wire rst_n,
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/* Data Input */
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output reg in_data_ready=0,
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input data_write_req,
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input [7:0] in_ascii_data,
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/* write circuitry */
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input wire done_writing,
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output reg write_req=0,
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output reg [3:0] data,
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output reg cmd_data=0
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);
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initial begin
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init_cmd_data[ 0] = 4'h3;
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init_cmd_data[ 1] = 4'h3;
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init_cmd_data[ 2] = 4'h3;
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init_cmd_data[ 3] = 4'h2;
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init_cmd_data[ 4] = 4'h2; //0x28
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init_cmd_data[ 5] = 4'h8;
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init_cmd_data[ 6] = 4'h0; //0x07
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init_cmd_data[ 7] = 4'h7;
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init_cmd_data[ 8] = 4'h0; //0x0C
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init_cmd_data[ 9] = 4'hC;
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init_cmd_data[10] = 4'h0; //0x01
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init_cmd_data[11] = 4'h1;
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init_cmd_data[12] = 4'h0; //0x06
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init_cmd_data[13] = 4'h6;
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init_cmd_data[14] = 4'h0; // 0x02
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init_cmd_data[15] = 4'h2;
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end
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reg [4:0] init_seq=0;
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reg [5:0] data_write_wait_counter = 0;
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reg [3:0] init_cmd_data [15:0];
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reg byte_n=0;
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reg data_write_latch=0;
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reg [7:0]print_data;
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always @(posedge clock,negedge rst_n) begin
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if(rst_n==0)begin
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in_data_ready<=0;
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write_req<=1'b0;
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init_seq<=5'd0;
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data_write_wait_counter<=6'd0;
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byte_n<=1'b0;
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cmd_data<=1'b0;
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end else if(done_writing)begin
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if(init_seq!=5'd16&&data_write_wait_counter==6'd0)begin
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data<=init_cmd_data[init_seq[3:0]];
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init_seq<=init_seq+5'd1;
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write_req<=1'b1;
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data_write_wait_counter<=6'd50;
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in_data_ready<=0;
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end else if (data_write_wait_counter!=6'd0) begin
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data_write_wait_counter<=data_write_wait_counter-6'd1;
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write_req<=1'b0;
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in_data_ready<=0;
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end else if(data_write_req==1&&data_write_latch==0)begin
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data_write_latch<=1;
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print_data<=in_ascii_data;
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in_data_ready<=0;
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byte_n<=0;
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end else if(data_write_latch&byte_n==0)begin
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data<=print_data[7:4];
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write_req<=1'b1;
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data_write_wait_counter<=6'd50;
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byte_n<=1;
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end else if(data_write_latch&byte_n==1)begin
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data<=print_data[3:0];
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write_req<=1'b1;
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data_write_wait_counter<=6'd50;
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byte_n<=0;
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data_write_latch<=0;
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end else begin
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cmd_data<=1;
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in_data_ready<=1;
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end
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end else begin
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write_req<=1'b0;
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in_data_ready<=0;
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end
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end
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endmodule
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