Efthimis/9086
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 1 Wiki Activity

Added STOS instruction. Native brainfuck compiler started generating code!

Browse Source
This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-24 05:01:55 +00:00
parent e684db8348
commit a189da249c
4 changed files with 34 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
system/decoder.v
View File

@ -445,6 +445,18 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
PARAM2=2;
seq_addr_entry=`UCODE_RET_ENTRY;
end
11'b1010101x_xxx:begin
/* STOS - Write byte/word to [DI] and increment accordingly */
/* | 1 0 1 0 1 0 1 W | */
`start_unaligning_instruction
opcode_size=0;
has_operands=0;
Wbit=CIR[8:8];
Sbit=0;
RM=101;
seq_addr_entry=`UCODE_STOS_ENTRY;
PARAM2=(Wbit==1)?2:1;
end
default:begin
`invalid_instruction
end
@ -477,7 +489,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
endcase
reg_read_port1_addr=ucode_data[25:22];
IN_MOD =ucode_data[28:26];
reg_read_port1_addr=ucode_data[32:29];
reg_read_port2_addr=ucode_data[32:29];
end
end

16
system/processor.v
View File

@ -112,18 +112,18 @@ reg [2:0] IN_MOD;
reg [2:0] OUT_MOD;
mux4 #(.WIDTH(16)) MUX16_1A(
PARAM1,
reg_read_port1_data,
{ProgCount[14:0],unaligned_access^unaligning_instruction},
16'b0000000000000000, /*0 Constant*/
/*0*/ PARAM1,
/*1*/ reg_read_port1_data,
/*2*/ {ProgCount[14:0],unaligned_access^unaligning_instruction},
/*3*/ 16'b0000000000000000, /*0 Constant*/
in_alu1_sel1,
ALU_1A);
mux4 #(.WIDTH(16)) MUX16_1B(
PARAM2,
reg_read_port2_data,
{ProgCount[14:0],unaligned_access^unaligning_instruction},
16'b0000000000000000, /*0 Constant*/
/*0*/ PARAM2,
/*1*/ reg_read_port2_data,
/*2*/ {ProgCount[14:0],unaligned_access^unaligning_instruction},
/*3*/ 16'b0000000000000000, /*0 Constant*/
in_alu1_sel2,
ALU_1B);

9
system/ucode.txt
View File

@ -17,6 +17,8 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
//rr2: reg_read_port2_addr
//
//imd: IN_MOD
//
//rr1: reg_read_port1_addr
@ -49,11 +51,18 @@
@000 0000_000_000__00__00_0000__00_000000
// 32 28 25 21 18 15 13 11 7 5 0
// CALL
// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@001 0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
@002 0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
@003 0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
// RET
// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@004 0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
@005 0000_011_1100_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
// STOS
// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@006 1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
@007 zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI

3
system/ucode_header.v
View File

@ -19,9 +19,10 @@
`define UCODE_ADDR_BITS 5
`define UCODE_DATA_BITS 33
`define UCODE_SIZE 6
`define UCODE_SIZE 8
/* DEFINE ADDRESSES IN THE MICROCODE */
`define UCODE_NO_INSTRUCTION 5'b00000
`define UCODE_CALL_ENTRY 5'b00001
`define UCODE_RET_ENTRY 5'b00100
`define UCODE_STOS_ENTRY 5'b00110