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Fixed bug found by icarus verilog and added outdated notice to README

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(Tim) Efthimis Kritikos 2023-05-16 13:59:16 +01:00
parent bfa576e2a0
commit 97912b1a29
2 changed files with 2 additions and 1 deletions
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1
README.md
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@ -28,6 +28,7 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview
This image is outdated. It was made for v0.1.0
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### License

2
system/processor.v
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@ -195,6 +195,7 @@ always @(negedge reset) begin
end
always @(posedge reset) begin
proc_state <= `PROC_RESET;
valid_instruction_ack <= 0; // needs early init
end
/*** Processor stages ***/
@ -214,7 +215,6 @@ always @(posedge clock) begin
SIMPLE_MICRO <= 0;
proc_state <= `PROC_DE_STATE_ENTRY;
owe_set_init <= 0;
valid_instruction_ack <= 0;
end
`PROC_DE_STATE_ENTRY:begin
if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin